too.
Do you like Spice too? Try taking a routing path and re-spicing with
20% lower metal capacitance. Either your chips have no metal in them or you'll see an improvement in delay with low-k.And yes, we have measured the difference in silicon. We fabbed Stratix in FSG and low-k; this was part of our qualification and testing of low-k. We didn't ever ship these low-k Stratix devices because we had sufficient yield into our fast devices. But we measured a performance advantage matching our expectations.
leakage
At worst we're talking about a 1W difference in 2S180-sized part, for worst-case leakage. How much dynamic power is being consumed in a chip that size? In the vast majority of applications it will be a fair bit
-- somewhere in the 5-10W vacinity wouldn't surprise me. Our dynamic power advantage on logic/routing, RAMs, DSPs, and especially I/Os will cover the difference in static power.
And where are those V4 worst-case leakage specs? It seems that you don't really have a handle on static power if a year after a product introduction you still don't know how bad it can be.
BTW, did you notice that the 2S60/LX60 devices used in your recent net seminar had the same static power (extrapolate from the dynamic power data)? And I love how you imply that our 2S90 chip you tested is out-of-spec on leakage, when in fact it falls between our "typical" and "worst-case" spec.
Regards,
Paul Leventis Altera Corp.