Stratix II vs. Virtex 4 - availability & fab partnership

Responding to comments on device availability and fab partnership . .

Stratix II Availability: Altera has a track record of shipping devices on schedule. We realize the importance of delivering products on schedule to minimize our customers' risk to deliver their end products. Altera has worked with TSMC, worldwide foundry leader, on 90nm process technology since 2001 and taped out >10 test chips prior to Stratix II. As a result, we were able to ship our first 90nm Stratix II device, the EP2S60, 6 weeks ahead of schedule. Stratix II development boards are available today. 4 additional Stratix II devices are on schedule to roll out before the end of the year and the final Stratix II device is on track for a Q1-05 introduction. And Stratix II devices are on boards at over

60 customers. 90-nm Fab Partnership A key component of any architectural selection decision involves probability of success in rolling out the devices. I agree with the general assertion made by my colleague that past success does influence this probability. Past success is based on picking the right fab partner, investing heavily with that partner, and staying on primary process nodes with mainstream processes. Argument was made that success on a proven 90 nm partner UMC (with Spartan 3) explains why Virtex 4 is low-risk. The fact that Xilinx's technical spokesperson has repeatedly highlighted that all of Spartan-3's availability woes are "demand related" and not "supply related" is also relevant here.

Altera will continue to invest all process related resources with a single partner, TSMC. This partner continues to demonstrate process excellence at every leading node. By investing with a single fab partner rather than diluting investment across multiple partners, Altera will continue to stay ahead of the process curve.

Altera will stick with mainstream processes and release product on them when they are ready for mainstream production. All 90-nm products will include low-K; now that low-K is mainstream and provides significant upside in terms of power and performance, it is clearly an advantageous feature. Triple oxide deviates from standard processing which seems ill-advised.

Spartan-3 delivery problems are not a demand issue. Spartan 3 unit shipments are below Spartan 2 unit shipments (I base this on publicly highlighted numbers) - perhaps Xilinx could point out the specifics here. And Spartan 3 unit shipments are ~ 1/4th Cyclone unit shipments (both parts rolled out at the same time). Clearly high-volume families are architected to expand the FPGA market; claiming "best rollout ever" or "demand problem" just doesn't line up with the facts.

And even if Spartan-3 90-nm issues were suddenly solved, this UMC "success" would only be relevant if Virtex 4 used the exact same fab process and fab partner for production. Current rumors in the trade press highlight that Xilinx is evaluating other sources for their

90-nm products (no doubt based on the tremendous success with the Spartan-3 rollout). I look for Xilinx to comment on which fab will be used for producing Virtex 4 parts.

I would strongly prefer to leave this site to the technologists. Altera will continue to respond though with marketing oriented postings when the facts are not properly presented or when marketing questions arise.

Dave Greenfield Sr. Director of Product Marketing ? High Density FPGAs Altera Corporation

Reply to
Dave Greenfield
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After reading the third post on this newsgroup, I realize the issues involved. You're SENIOR marketing "professional" - a director? - who should know that ENGINEERS - the primary customers - don't respond well to marketing CRAP even if it comes from Xilinx. This newsgroup hasn't been poisoned by continuous marketing blather. The professions who *do* deliver information on this newsgroup - Altera and Xilinx both noted - usually keep the marketing to a minimum though sometimes the company line gets to them so strong that something slips.

The cost/performance advantages that the Altera devices can provide (versus the cost/performance advantages that the Xilinx devices deliver) are turning my perceptions back toward my Altera roots. You are doing a SEVERE DISSERVICE to the local rep and FAE who are trying to win back my business by being a sincere marketing ass (in keeping with the republican/democrat mindset).

Please produce whitepapers on the Altera website and highlight those papers on the Altera home page if you hope to keep the respect of anyone sitting on the fence.

Reply to
John_H

Obviously V4 has you on the defensive big time! Three long winded posts in one day. Nice to see. It's back to the days of Virtex II vs. Apex II. I'm sure you will enjoy it this time as much as you did back then.

How hard is it to tape out a product family that has no new innovation from the previous family? Stratix II is simply a copy and paste from Stratix. Except for the ALM which is still only a partial copy of the Xilinx CLB. Only a partial copy because you still don't have distributed RAM or SRL 16 capability. Both very useful and commonly used features. If your new ALM is so gosh darn awesome, why didn't you put it into Cyclone II?

Spartan 3 yield issues are solved and Spartan 3 is simply dominating out there. That's the truth. Now Virtex 4 is going to dominate as well. It has tons of new innovation poured into it.

1 Gbps serdes on EVERY user I/O 78 ps delay adjust on EVERY user I/O up to 17 I/O banks EVERY I/O standard on EVERY user I/O XCITE on chip termination (both serial and parallel) .6 to 11 Gbps Rocket I/O Built in FIFO logic Built in 10/100/1000 EMAC Power PC

My fingers are tired of typing now but the list goes on and on.

Reply to
Stifler

Hi Stifler,

Well, at least David included his affiliation/credentials. But let's take a quick (admittly fun) poke at your message.

It wasn't hard at all. I took a two-year vacation and watched my curser blink between table tennis matches. When time was up, I just copy and pasted my Stratix code and schematics, did a search and replace for the word "Stratix", and I was finished. Same goes for the other hundreds of engineers working on the product. But when transferring the masks to TSMC by our patented Carrier Pigeon technique, the high altitude and resulting exposure to radiation resulted in random mutations. The unfortunate outcome was a product 50% faster and 25% more dense than Stratix.

Don't worry -- our rad-hard pigeon survived.

Most engineers should be able to examine a block diagram of a CLB and ALM and see that they are fundamentally different logic structures -- perhaps the location of your head is obscuring your vision? If you care to learn more, please refer to my previous posting on the subject (see

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.

Different markets, different performance/area trade-offs.

Yield issues -- I thought there was just too much demand ;-)? And are you referring to the enormous performance deficit vs. Cyclone, or the 1M cumulative units of S-3 sold as of today compared to 2M for Cyclone back in March? But that's enough marketing blather from me.

I hope your fingers recover so that you may continue to contribute to this newsgroup; I'm sure we'd all miss you otherwise.

Warmest regards,

Paul Leventis Chief Carrier Pigeon Officer Altera Corp.

Reply to
Paul Leventis (at home)

Um...you are all making good points, but I think the technical folks in the crowd do not care. I suggest you organize some sort of mud wrestling event and see which of you can sell more tickets for bragging rights.

. . .

Reply to
Chris Alexander

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