Responding to comments on 90-nm power . . .
Claims here are challenging to understand. It appears that Xilinx suggest power goes down by 50% at the same time performance doubles, due mainly to a triple oxide process (benefit to leakage power) and embedding hard IP (benefit to dynamic power). Let's take a look at these claims.
Leakage and triple oxide: Xilinx claims triple oxide is used in CRAM to reduce leakage current by 50%. In Stratix II, CRAM accounts for 5% of total leakage. Does this imply CRAM leakage in Virtex devices had been 50% of the chip's total leakage? Current collateral also glosses over the tradeoffs of triple oxide, which the rest of the industry (including the likes of Intel, TI, IBM, etc.) have analyzed and have deemed too risky and too costly at 90nm for the small benefit provided. Triple oxide adds die size (larger transistors). It also requires ~4 more wafer processing steps. Both of these aspects increase the wafer cost. Both of these factors also reduce yield. Because there are now not two, but three different oxides it takes longer to tighten up the process and thus deliver sustainable, regular yields (i.e. guaranteed delivery). Finally, rapid yield enhancement requires driving wafer volume, but the limited use of triple oxide at either UMC or some other potential foundry highlights that Virtex 4 may be stuck driving the triple oxide yield enhancement alone.
Dynamic power and the benefits of embedding more hard IP: Xilinx suggests dynamic power goes down by a factor of 7x by embedding hard IP. The Virtex 4 documentation suggests the new multipliers run up to500 MHz and consume only 57 uW/MHz. In the SX55 device (with 512 multipliers), that is 15 W of dynamic power just for DSP. Dynamic power for the core, RAMs, and I/O, and then leakage are on top of this. I'll assume the 7x factor likely doesn't apply here. Low-k helps reduce dynamic power by about 10% and gives a boost to performance of ~ 10% (part of Altera's power reduction arsenal). It doesn't look like Virtex 4 will get this low-K benefit.
There are other process techniques besides triple oxide to reduce leakage power. For instance, Altera implements different Vt's using different implants to reduce leakage power. This is how we get a low leakage CRAM. It is safer than triple-oxide, and yields leakage power reductions that are quite similar. We also judiciously apply non-minimum length transistors. Configuration RAM is a solved problem since there is no performance requirement, we can use both these techniques to greatly reduce sub-threshold leakage.
The Stratix II ALM is power-friendly. (1) It reduces the number of logic levels, so we can use lower leakage routing transistors and maintain speed. (2) It reduces the amount of routing needed by absorbing more logic into the larger logic functions, so we replace the still-somewhat-leaky routing transistors with low-leakage CRAM cells.
My assessment is that Virtex 4 is primarily trying to get power reductions through process techniques, while most of the semiconductor industry has concluded this is not sufficient -- you also need to get gains at the architecture level.
Dave Greenfield Sr. Director of Product Marketing ? High Density FPGAs Altera Corporation