vertex II vs Stratix

Andy,

What are you trying to do?

It is very hard to compare something when no one knows what the application is.

For example, if you need embedded ultra low power 32 bit RISC >400 MIPs processors, there is no choice other than VII Pro with up to two IBM

405PPC (tm).

Or, if you need twenty 10 Gbs interfaces, there is no choice other than the 2VP70X.

And we misspell it Virtex(tm) on purpose so we could trademark the name.

Aust> Hi everybody, Could you people help me choose between Altera's Stratix

How do you choose between a Toyota and a Honda, or between a Mercedes and a BMW ? You have to study the documentation, and get beyond the common features, then evaluate the differences, and find out what's most important tofor you. You might also read the marketing literature, but you have to realize that marketeers will only dwell on the positive aspects, and they might occasionally even stoop so low to exaggerate... It's Application's never-ending job to keep them honest. Peter Alfke ======================================

If you have a design underway, one method is to take a representative chunk of that design and implement it, using the free tools (or the real tools with an evaluation license) for that architecture. I needed arithmetic, so I chose a square root unit as a non-trivial test.

That will give you a basis for comparing gate counts, speed, capacity,

-and the reliability and usefulness of the tools- for both architectures.

- Brian

Hi, Andy,

There are many things that will affect the optimal FPGA selection for your design including core performance, DSP capability, high-speed memory interfaces, clocking requirements, etc. not to mention the vendor specific development tools. I have been working on benchmarking Altera versus Xilinx and there are varieties of design and tool flow issues that will affect your result.

When you benchmark, you will need to control the tool effort level (fast or exhaustive), software settings, timing constraints and clocks analyzed. These settings can cause results to change by up to 3X based on our benchmarks so understanding these options is fundamental to making a good performance comparison. In addition, you will need to be careful if your design is coded to take advantages of specific features in a FPGA.

These issues will be discussed in a net seminar hosted by Altera on April 8th regarding effective FPGA performance benchmarking methodology and comparison of leading FPGA architectures. If you are interested, the registration link is here:

John Hu Altera Corp.

All,

Benchmarks can be organized to demonstrate just about anything you want. We try to be as fair as possible, as we are interested in evaluating the strengths of the competition, not just the weaknesses.

Caution!

Since the VII Pro is 40% faster than Stratix, and Stratix Two will be (as claimed, once they have silicon and test it) to be 50% faster than Stratix One, that makes Stratix Two roughly at parity with Virtex II Pro from Altera's claims when compared against our extensive 200+ simulations of customer designs thru both sets of tools using real speeds files from 2+ years of silicon.

We will release the results of our suite of 200+ actual customer designs results being pushed thru the respective tools soon. So at that seminar, ask:

how many designs? where did they come from? do they target device specific features? how much of the part is being used? what is the speed data based on?

If the answers are not: 200+, customers, yes, all (>80%), and real silicon, then 'caveat emptor'.

So, for what it is worth, the two parts look like they are going to be roughly equivalent in fabric performance.

Virtex II Pro also has (today) the 405PPC, the MGTs, the DCMs, and the SRL16s.

One maxim of marketing is to take whatever you think you are strong in, and the competitor is weak in (real or imagined), and make that the issue. Don't talk about anything else. Bang the drum with a loud and consistent message. Hey, that is fair. If the fabric is predicted to be at parity, or slightly better, make a big deal out of it.

I prefer to analyse all the strengths and weaknesses as an engineer, and see how that relates to my application.

Stratix Two will be 90nm technology.

Virtex II Pro is 130 nm, and going on 2 1/2 years old right now.

Virtex 4 (the 90nm version) is yet to be revealed, and that would be the real apples to apples product face-off. In my opinion, the 90nm parts should outperform the 130 nm parts (or why bother?). The dissapointment is that it appears that it will be only one speed grade faster in the fabric, and still lack many features. So, if you want speed, just order one speed grade faster in 130 nm today!

Austin

URKH! Do we really need aggresive marketing wars in this newsgroup?

--
	Sander

+++ Out of cheese error +++

Sander,

I apologize if I have offended. Just wanted to be sure to balance the scales.

Austin

I agreed. I was in Altera web seminar. I asked "Stratix is only comparable to Virtex-II, not -Pro" and did not get answer.

I do not have comments on the performance comparison materials. But my designs required 190 16x16 multipiliers in each of three FPGAs in a row. Stratix had no way to do it. Stratix-II, too later.

I really think Xilinx's claims ISE 6.2 40% over 6.1 50% over 5.2 70% over 4.x ..... were jokes. I was seeing -1000% 6.2 over 6.1.

-qlyus

no offence, I just think pure marketing - and even more so aggressive marketing asking people to question various things doesn't IMHO really belong here. This isn't to pick on Xilinx or you.

--
	Sander

+++ Out of cheese error +++

Sander,

Thanks, I just can't stand it when others post "PM" so I feel obligated to balance it out.

I do try to place some really useful and practical bits in the post, however.

Aust> Aust>

qlyus,

If you get such a degraded performance result, you should open a case. That is an indication that something is not right. Either your style is using the wrong features, or the software is. We certainly like to know.

Any individual design can easily vary 2:1 in performance on either toolset, so just as one error does not define a rate, one result does not define performance.

Just curious, what do you use 190 multipliers for, and what is the market for that?

Aust> I agreed. I was in Altera web seminar. I asked "Stratix is only

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

It is a Multirate application. The data is coming directly from an ADC chip running at over 1GHz sampling rate, 4x upsampled, then pass through multiple stages of FIR filters to have various rates in output. Because of the data rate, we have to build multiple filters in parallel. 190 multipliers are used for only 8 93-tap filers in parallel in one stage.

I tested one of the designs in ISE 6.2. It was just one stage block of such filtering, flip-flops for data pipeline, multipliers, pipelined adders. ISE started in edif file without timing and LOC constraints. The design had a single clock domain. The PAR in 6.2 took a half to one hour to finish.

ISE 6.1 ran only about 5 minutes, even with 150MHz clock constrained.

Anyway, I stay with ISE 6.1 until 6.2 sp#2 comes out to try.

May I ask you a question not related to this topic, Austin? Some of the LVCMOS25 inputs in Virtex-II Pro are driven by 3.3V LVTTL signals from other devices. We have noticed that the clamp diodes in these LVCMOS25 inputs are activated and the voltage levels have ramp started at ~2.7V and are clamped at 3.0V. It seems these 3.3V drivers are not strong ones (like line driver with +/- 24mA capability) since their datasheeds specify Voh/Vol only at Io=0.5mA or so. But we have no way to figure out how much the exact current is driving into the diodes. Are these inputs of Virtex-II Pro safe in a long time? Thanks.

-qlyus

designs with

meeting timing on all

with the effort

figures to be the

The place and route tools work with timing paths and don't distinguish between whether they are in the same clock domain or not. Minimizing clock skew could have an effect on timing within a clock domain and could possibly make timing between domains worse, but we'd have to look at the design to see if that's the case here.

We never said that. 6.2i results are an average of 2% faster than

6.1i. The 40% was V2Pro over Stratix.

I'm not sure where these numbers came from. Usually, we get around a

15% average increase each year. Sometimes we also report a number like "map -timing can get you up to 40% better results". In this case, map -timing doesn't help much unless the design is full and packing unrelated logic, so reporting an average would be less useful.

We ran hundreds of designs on 6.2i and never saw anything worse than

-5%. Please send the design to our hotline and we'll take a look at it.

Steve

Austin,

To your comment: "Just wanted to be sure to balance the scales." What exactly were you looking to balance? The only related post was John Hu's posting that was a completely technical reply (i.e. no marketing data or performance comparison whatsoever) to a request for information comparing Virtex II with Stratix. John also provided a pointer to where the user could get information if he was interested. Your post seemed like a bit of a preemptive strike against content in a net seminar ? not information on this site.

And "just can't stand it when others post "PM" so I feel obligated to balance it out". While I don't know what "PM" means, there was no applicable follow-up post here whatsoever. Don't confuse a net seminar (where some degree of marketing is generally acceptable) with a post here.

Altera will respond to technical issues on this newsgroup (ideally Altera's increased activity over the past 18 months has positively contributed to this group). We will generally refrain from providing marketing information here ? though we may point requesters to a location where they can get marketing data. However, we will selectively respond with marketing information where it is warranted (i.e. when responding to direct competitive questions, incorrect information, or competitor's claims).

And this certainly applies to postings from any individual who consistently uses a cloak of being just a technical person while regularly dishing marketing data.

Dave Greenfield Altera Product Marketing

Thanks, I just can't stand it when others post "PM" so I feel obligated to balance it out.

I do try to place some really useful and practical bits in the post, however.

Austin

Dave,

As a third party observer, I felt that Austin's preemptive strike was justified given that the link was posted in the newsgroup. Likewise, I would have no problem with you directly answering the questions he raised. I may get myself in trouble here by violating the technical sanctity of this newsgroup, but I think some marketing (with technical or factual points) can be useful as long as it does not interfere with the specific technical questions posted.

I had three points relating to the seminar in question that I hope you can address:

1) Was I/O timing taken into account at all for the benchmarks? Did the designs have I/O constraints? I would have liked to see both the Tsu and Tco on the critical path, instead of just the Fmax, since these can be traded off in many situations. In fact, a higher core Fmax at the expense of system Fmax may be useless in many applications.

2) How long has Altera had these 75 designs? Part of the discrepancy in performance between the two vendors may be that the tools, and possibly even the architectures, have been tuned to their in-house designs.

3) For your "best effort" comparision, did you use any manual placement/routing for either of the tools? Did you analyze the critical path of either vendor for possible improvement through manual intervention?

SD

Dave,

As a third party observer, I felt that Austin's preemptive strike was justified given that the link was posted in the newsgroup. Likewise, I would have no problem with you directly answering the questions he raised. I may get myself in trouble here by violating the technical sanctity of this newsgroup, but I think some marketing (with technical or factual points) can be useful as long as it does not interfere with the specific technical questions posted.

I had three points relating to the seminar in question that I hope you can address:

1) Was I/O timing taken into account at all for the benchmarks? Did the designs have I/O constraints? I would have liked to see both the Tsu and Tco on the critical path, instead of just the Fmax, since these can be traded off in many situations. In fact, a higher core Fmax at the expense of system Fmax may be useless in many applications.

2) How long has Altera had these 75 designs? Part of the discrepancy in performance between the two vendors may be that the tools, and possibly even the architectures, have been tuned to their in-house designs.

3) For your "best effort" comparision, did you use any manual placement/routing for either of the tools? Did you analyze the critical path of either vendor for possible improvement through manual intervention?

SD

Hello,

Welcome aboard, Dave.

In this context PM appears to be Pure Marketing.

I for one have been delighted to see more Altera presence at this group. Greg, Vaughn, Paul, Hong and others have provided valuable support in this forum.

It bears mention, however, that I have a paid Quartus subscription and an active mySupport account ! Yet the caliber of support I can get here, both from Altera and non-Altera folk, far surpasses what your company sees fit to provide through mySupport.

For example, I posted 4 mySupport requests during the month of March. One generated a response "I submitted a Software Problem Report for this issue. It will be resolved in a future release of DSP Builder". Another -- in regard to AsyncClear on registered ports of Stratix memory blocks -- got me after 3 weeks a response "Asynclear is not support is stratix memory block", which I believe to be factually in error. The other two queries are gathering dust.

The upshot of this is that you have a user like myself, who is happy with the Stratix chips and likes the Quartus software, yet I would not hesitate to do my next design in Xilinx.

I for one have not been put off by marketing content from Austin, nor for that matter from your colleagues at Altera.

And here is a marketing question for you:

What are Altera's plans with regard to DspBuilder ? I find it a buggy product, to the point where I find it amazing that it has been brought to us by the same team that brought us MaxPlusII and Quartus II -- both of which are truly first-rate. Is DspBuilder going to languish as a marketing counterpoint to Xilinx SystemGenerator, or is it going to brought up to the standard of Quartus ?

Sincerely,

-rajeev-

Oops ! Left Subroto out.

-rajeev-