I have a very simple design that uses 3 LEs in Stratix when compiled with either Quartus II 4.0 or Synplify. There must be something I don't realize about the LE/routing architecture because I think it should/could use only 1 LE (see design below). I would think the design should connect the four terms to the 4 inputs of the LUT, feed this LUT's output to the D-input of the register of the same LE, and also connect the enable and reset of the register with the respective inputs.
Here's what it does instead: Routes the 4 terms to its own LUT, then ANDs the LUT's output with the enable input in a 2nd LE and fianlly uses this result as the enable of the register in a 3rd LE. The D-input of this register is tied to VCC. Seems very odd to me.
In Quartus, I turned on Optimize Area, Auto Packed Regs=Minimize, and played with a few other options, to no avail. Setting the fmax sufficiently high packed the design into 2 LEs but did it in a wierd way. I'm curious why the design doesn't ever route into 1 LE?
library ieee; use ieee.std_logic_1164.all;
entity test_4input is port ( clk : in std_logic; -- should go to LE's reset: rst_n : in std_logic; ena : in std_logic; -- four terms: a, b, c, d : in std_logic; result : out std_logic ); end;
architecture rtl of test_4input is signal sig : std_logic; begin
process( clk, rst_n ) begin if rst_n='0' then sig