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Stratix II basic questions

Hi,there is any Stratix II user here?

I'm involved in a hardware design for an EP2S90 device. I didn't ever used such a beast but I have some serious background in analogic/logic/RF design. I've downloaded everything I found from the Altera site but the information is huge and not very well organised in those books. The questions would be:

- which is the most common configuration methode you'll choose for a Stratix II (would be the AS a good choice or better the PS, assuming there is a PCB space constrain and starting time is not an issue)

- for an active serial configuration: a. you'll use the download cable port for the serial FLASH config device every time you'll change the configuration ? or b. you may change the configuration with the JTAG for software test purposes and burning the flash will be the last operation and it will be quite rarely ?

- how you'll choose the input and output ports (regarding to banks and quadrants) if you'll need to implement a complex math including DSP operations (FIR, matrix, etc) ? c. there are restrictions for such operations in using the banks of one quadrant for input and banks from other quadrant for the outputs (or banks for the same quadrand, but using huge number of LABs from different quadrant d. there are restrictions in sending data from one quadrant to other quadrant ( like from Q1 to Q3 for example?

- how you'll use the FPGA (and clocks) if a part of it must act as a FIFO between two different speed systems

any help appreciated thx, Vasile

Reply to
vasile
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It depends what else is on the board. If there is a cpu and flash file system, loading the fpga image is just one of many initialization tasks, and I can ftp an fpga image file directly to the embedded kernel whenever I like.

I like to write and sim the hdl code first and then let place and route take the first cut at picking pins.

-- Mike Treseler

Reply to
Mike Treseler

There is a DSP and a parallel flash memory used for DSP bootloader or program holder (and a lot of other stuff). Sharing the same Flash memory between the FPGA and DSP is a hard task because on FPGA initialisation the bus must be released by DSP.

But if this job will be done by someone else ?

Thx Mike,

Vasile

Reply to
vasile

I would use a few ports bits from the DSP to load the FPGA. No need to share the bus.

I would wait until that "someone else" had working code before I started a circuit board.

-- Mike Treseler

Reply to
Mike Treseler

Hi Guys, FWIW, here's my 2 cents. I prefer to let the PCB layout person decide the detailed pinout. One reason I do this is because the routing resource in the FPGA is cheaper than on the PCB. Also, I find that signal integrity can be compromised by having to route PCB signals according to the P&R method. So, I tend to place the major components on my PCB, use that to guide on which banks I have which signals, but then let the exact pinout be decided by the PCB routing requirements. Then start my RTL design while someone is making the boards. HTH, Syms.

Reply to
Symon

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