ASMBL

While waiting for the next announcement.... perhaps some Xilinx person could answer these questions?

Crista Souza's and Ron Wilson's piece in EETimes says in the final paragraph:

The column-based approach means that IP companies that either license to Xilinx or want to be acquired will

**now have precise physical constraints for how to incorporate their IP into Xilinx FPGAs**. Initially, that will whittle down the field of qualified vendors, but ultimately it will result in higher-quality IP, analysts said.

Whom should one contact to find out more about these precise physical constraints?

Will it require the IP companies to work with expensive ASIC design and verification software, or will there be some new software which has the parameters which the designers can use already set up for the base platform and taking into account these constraints?

Thanks

Shiraz.

Reply to
Shiraz Kaleel
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Shiraz,

Idle speculation on the part of over-anxious authors?

Aust> While waiting for the next announcement....

Reply to
Austin Lesea

I'm left puzzled as to why they should be anxious ? Maybe over-excited, or over-hyped, but anxious ?!

The cited reason for the ASMBL early info release is to 'create interest'.

Well, Ok, it's done that......

Now, imagine this :

Interest generates questions, and when those questions are given a 'wait and see' reply, that interest changes to annoyance and frustration, and the market droids 'clever idea' morphs into one needing damage control...

Still, those looking for hard info on future FPGA directions could, of course, pop over to

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-jg

Reply to
Jim Granville

Jim,

anxious -

"1. Uneasy and apprehensive about an uncertain event or matter; worried. 2. Attended with, showing, or causing anxiety: spent an anxious night waiting for the test results. 3. Usage Problem. Eagerly or earnestly desirous.

[From Latin nxius, from angere, to torment. See angh- in Indo-European Roots.]anxious·ly adv. anxious·ness n.

Usage Note: Anxious has a long history of use roughly as a synonym for eager, but many prefer that anxious be used only when its subject is worried or uneasy about the anticipated event. In the traditional view, one may say We are anxious to see the strike settled soon but not We are anxious to see the new show of British sculpture at the museum. Fifty-two percent of the Usage Panel rejects anxious in the latter sentence. But general adoption of anxious to mean ?eager? is understandable, at least in colloquial discourse, since it provides a means of adding emotional urgency to an assertion. It implies that the subject so strongly desires a certain outcome that frustration of that desire will lead to unhappiness. In this way, it resembles the informal adjective dying in sentences such as I'm dying to see your new baby."

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Austin

Reply to
Austin Lesea

Oops, I missed one - in addition to

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more FPGA direction indicators are also here :-

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As to anxious, anxiety, or over-anxious etc, perhaps the subject "ASMBL anxiety" says it all... :)

-jg

Aust> Jim,

Reply to
Jim Granville

Jim,

*

*.......I have been admonished for commenting on competitors in this forum. That will have to be left up to others like yourself.

A careful review of all of the features of St2 will have to be left to others.

Perhaps Ray Andraka can comment on their new ALM architecture? Advantages, disadvantages?

Aust> Oops, I missed one - in addition to

Reply to
Austin Lesea

One thing that was not obvious in a quick trawl thru their info, was the relative NIOS sizes (Stratix / Stratix II). You'd think that would make a good benchmark, but maybe it's still a 'work in progress' as they tune the SW.

Anyone seen actual numbers or NIOS or NIOS II ?

-jg

Reply to
Jim Granville

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

I did a quick compile in Quartus2_ver4 with Stratix2 and Stratix same Nios design only changed parts. Results in ALUT's compared to LE's is

3202 ALUT (S2) and 4522LE's (S). Push button compile of design no tweaking no logiclock. Cheers Fredrik
Reply to
Fredrik

Hi Fredrik,

Are these numbers for a 32-bit Nios with hardware multiply?

-- Pete

Reply to
Peter Sommerfeld

Hi Pete,

No hardware multiply (used MSTEP), but 32-bit Nios. Design used was one I used on some Nios traning with DMA and a CRC custom istruction in it. Also some other goodies for trying out the various features of the Nios Stratix board. Cheers Fredrik

Reply to
Fredrik

Jim,

Nios v3.2 is the final release of "classic" Nios. It is slated to be released very soon, and will offer a couple of tweaks for Stratix II support. For another data point: I ran the "minimal_32" example through QII 4.0 for both device families and got 2011LEs (Stratix) vs.

1393ALUTs (Stratix II).

Again, Nios 3.2 will officially support Stratix II.

As for Nios II... I cannot comment on that yet, but stay tuned, its worth waiting for.

Jesse Kempa Altera Corp. jkempa at altera dot com

Reply to
Jesse Kempa

Jesse, Thanks for that. We would expect NIOS II to be more 'tuned' for Stratix II...

Here's a question, (for when you can comment :) Will NIOS II have a variant that fits/runs on MAX II devices ?

-jg

Reply to
Jim Granville

Hi Jim,

I'd love to address that right now but can't -- stay tuned for the MAX II & Nios II launches. They will answer that question.

- Jesse

Reply to
Jesse Kempa

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