dear
i am using 'unisim' for Xilinx component for VHDL "simulation" in Modelim. So, as far we know the name of the component, no VHDL description (implementation) was required, which was convenient.
Now I am wondering whether it is possible to
- synthesize Xilinx component uing unisim only,
Should I use 'coregenerator' to synthesize?
Thankyou in advance
Yes. You do not actually have to synthesize the unisim components, and I never do (though I think they are synthesizable). Everything in the unisim library is a primitive, or a "primitive" macro. The Xilinx PAR (place and route) software understands the unisim names, and it will insert the proper construct.
Coregen is used to create non-primitive cores. That is completely different from the unisim library. If you are not used coregen generated cores in your simulation, then you won't use them in your synthesis.
No need to use coregen. Just use the corresponding instance name, the synthesis tool automatically recognizes it
Vladislav
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