Hi, I am a student, without much experience of synthesis. My task was to make some modifications (i.e. insert faults) to the ISCAS benchmark circuits and synthesize them to the FPGAs. I read the circuits using the ISCAS benchmark format - made my changes to the circuit structure and dumped out the VHDL.
My problem is that I cannot get this to synthesize with the standard tools for medium sized circuits i.e. they either run out of memory or they complain that my file is too long or something like that. (Circuits with a few hundred gates work fine - so I dont have a problem with syntax or somehting like that.) I wonder if there is a way out for me.
Initially I dumped each of the faults that I had inserted as separate entities. This made the number of entities that I used too large e.g. for a 10K gate circuit - I had a little more than 10K entities. Note that I did not increase the number of gates - but I just added additional Muxs (multiplexers) and some control lines. I was surprised that this modified circuit would not synthesize. XST (8.2) complained that it ran out of 4 GB of memory, Synopsis complained that the number of lines in my file were more than 1 million - this made me move some entities to separate files - but finally it also crashed.
Somebody then came along and told me that the synthesis tools require a lot of overhead for the entities. So I decided now to just put everything in one big global entity. Here also XST crashes after hitting the 4GB memory error.
A code sample showing one of my gates (with the associated Mux) is
Nand_2_0_0 : forg_node_16_Cell_0