dear
I implemented some multiprocessors and some routers.
3 processors exchange data via routers and store into local memory. Functional VHDL simulation in MODELSIM seems okay. The VHDL code is synthesizable. BRAM was the only Xilinx resource that I used.Now I need to verify in real hardware using implementing and mapping into FPGA (vertex II pro and BRAM).
My goal is only to see 'memory' value after 'data transfer' via routers.
As far I found, it seems there are two ways to do that. First, host and FPGA serially communicate using UART module and hyperterminal. Second, chipscrop pro core can be synthesized with my logic.
I am newbie on these things -: I am wondering what is more efficient, or if there is another way to see Block-RAM values.
If I use 'serial' communication, I could use Xilinx 'UART' module but question is that
- Can we see memory values on 'hyperterminal'?
If I use 'Chipscope pro', there seems too many cores (ICON,ILA,ATC,IBA,VIO), and area overhead seems too big.
Question is that
- What kind of Chipscope core do I need to see memory values?
- How much slices(CLB) those core consume?
- Are there any examplary tutorial for chipscrop to follow up?
Thankyou in advance