Hi all,
I was given an EDIF netlist for evaluation of IP core. I could synthesize it and see and everything. But i am unable to check functional simulation of the core as to how it works. Is there any way to do it with Modelsim and Xilinx tools
thanks in advance
and a after place and route simulationnal could'nt be good??
you could generate a post place and route with xilix fondation in implement project>place and route >generate place and route simulation model
it should generate you a model in vhdl that you can use in modelsim
alexis
a écrit dans le message de news: snipped-for-privacy@f14g2000cwb.googlegroups.com...
Hi all,
way
There isnt anyway to 'reverse engineer' the edif netlist to see what the original vhdl looked like using modelsim if thats what you mean.The best you can hope for is to look at the data flow of the edif to vhdl writer produced vhdl which isnt going to be easy and thats basically the whole idea.
You can convert the EDIF to a Verilog file. If you received an ngc file then you can do an ngc2hdl. If you received and edif then you have to do two steps, edif2ngd followed by ngd2ver.
Your synthesizer probably gives you the option of creating an HDL netlist. You may use this for a post-synthesis simulation.
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