Xilinx Spartan 3 CLB Slice Options - more detail than in datasheet available?

If you use a LUT as a 16-bit ROM (its normal application), then there is no benefit whatsoever in the ability to invert any or all of the 4 inputs, or the output. Anything you might do with inverters can be done by just redefining the 16 LUT bits. Clock enable Write Enable and Clock polarity may sometimes "need" inverters, but even that is rare. The LUT is a very versatile tool; that's why we are so loyal to it... Peter Alfke

Hi Peter, Thanks for your comments, I understand the LUT implements any boolean function of 4 variables(as well as 16x1 RAM, SRL, etc of course). But say I have a slice where the F-Lut and FFX(flop) are already used, and furthermore it is the F-LUT output that is routed to the FFX D input. If the underlying slice hardware provides for an invertor on the BX path say - then don't I have a "free" additional invertor that can be used with BX as the input and BXOUT as the output? This is additional logic than what is already provided by the LUT.

In case anyone is interested, what I am actually trying to do is take a

14 bit +ve number and convert it to floating point. For example, to find the exponent the first step is to use a priority encoder to find the position of the most signficant bit. I use the carry chain configured for "propagate-kill". Starting from the MSB a 1 is propagated down the carry chain until an input bit with a 1 is encountered, from then on the carry chain propagates a 0. One LUT controls the MUXCY carry propagation. The other LUT AND's the input bit and the input carry to generate the priority encoded output. I then encode the 14 bit priority encoded value to 4 bits that represent the exponent. I can do that encoding with 2 Luts per bit. I wish I could find some way to exploit the FAND, XORF or F5MUX to reduce the amount of LUTS required.....

Hmm if the inputs to the FAND could be inverted then don't we have a "free" 2 input LUT also in the slice? Of course that would make the carry chain unusable in that slice.

Regards Andrew

Peter Alfke wrote:

Hi Peter, Thanks for your comments, I realise the LUT can implement any boolean function of 4 variables (or SRL, 16x1 RAM, etc). But say the F-LUT and FFX Flop are both used (and the F-LUT output is connected to the D input of FFX). If the logic cell includes an invertor on the BX input, don't I effectively get this invertor for free and I can use it on the BX to BXOUT path? This invertor is additional logic than provided by the LUT.

Also, if invertors present on the FAND inputs then I get a 2input function generator for free? (obviously there are restrictions, F1, F2 must be the inputs, can't use the carry chain for something else - the output would come out XB.)

Or am I trying to push the Spartan 3 logic cell too far?

In case anyone is interested, what I was trying to do is find the floating point exponent(4 bits) for a 14bit unsigned number. I havn't spent a lot of time on it, but the best I have come up with so far is firstly a priority encoder to find the location of the MSB. The priority encoder is implemented with a "carry-propagate-kill" using the MUXCY and 2 LUTS per bit. (one LUT to control the MUXCY carry propagation and 1 LUT to generate the priority encoded output). I then use a further 8 LUTS to encode the 14 bit priority encoded value to a binary exponent(4 bits - 2 LUTS per bit). I feel like it would be nice to somehow make use of the FAND or XORF or F5MUX to reduce the amount of LUTS required but can't quite see how yet.....

Regards Andrew

Peter Alfke wrote: