Generic synthesis target in Synplify Pro

If your code is not synthesizable, you'll get stuck in the middle of stage

1. So steps 3-5 are not necessary to tell whether your code is synthesizable. Did I miss something?

Generally, if code is synthesizable for one chip it is synthesizable for any. Of course there will be exceptions to this, and the quality of the synthesis results will vary from device to device, but generally it's good or it's not.

Cheers,

-Ben-

Thanks guys.

Only one restriction comes to mind:

DDR logic (two clocks or both edges of one clock) will only synthesize to targets that have DDR resources (usually IO registers).

Arrays will (with the appropriate restrictions) synthesize to ram on devices that support it, or to registers on targets that don't, but they will always synthesize, regardless of the target.

Andy

Ben J>

rnbrady schrieb:

You need to select a target technology for synthesis. Some constructs are in principal synthesisable but only if your target technology supports these technique (like RAM,...). You might of course write your own generic lib, but it might be a bit oversized for your problem. On the other side it might be very interessting for benchmark reasons, maybe a lib containing only a 2NAND would be enough *g*.

bye Thomas