Dear
I want to synthesize "opb_arbiter" in ISE.
What I did was (1) Locate "opb_arbiter_v02_e" and "proc_utils_v1_00_a" (located in EDK directory) (2) Set up parameter : number of master = 4 (default) (3) Compile top module "opb_arbiter".
However an error occurs, as indicated in the source codes below.
/opb_arbiter_v1_02_e/hdl/vhdl/opb_bus_arbiter/onehot2encoded.vhd Error : or_bits is not an entity name
Let us know how to synthesize, if anyone has this experience. Thank you in advance.
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-- /opb_arbiter_v1_02_e/hdl/vhdl/opb_bus_arbiter/onehot2encoded.vhd
----------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- OPB_ARB_PKG includes necessary constants and functions
------------------------------------------------------------------------------- library unisim; use unisim.vcomponents.all;
library opb_arbiter_v1_02_e; use opb_arbiter_v1_02_e.opb_arb_pkg.all;
library proc_common_v2_00_a;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_1HOT_BUS_SIZE -- number of bits in the 1-hot bus
--
-- Definition of Ports:
-- Bus_1hot -- input 1-hot bus
-- Bus_enc -- output encoded bus
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
----------------------------------------------------------------------------- entity onehot2encoded is generic ( C_1HOT_BUS_SIZE : integer := 8 ); port ( Bus_1hot : in std_logic_vector(0 to C_1HOT_BUS_SIZE-1); Bus_enc : out std_logic_vector(0 to log2(C_1HOT_BUS_SIZE)-1) ); end onehot2encoded;
-----------------------------------------------------------------------------
-- Architecture section
----------------------------------------------------------------------------- architecture implementation of onehot2encoded is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- encoder logic requires that the 1hot bus be padded to next power of
2 constant PAD_1HOT_BUS_SIZE : integer := pad_power2(C_1HOT_BUS_SIZE);
-------------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------------- signal pad_1hot_bus : std_logic_vector(0 to PAD_1HOT_BUS_SIZE-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- OR_BITS is used to determine if segments of the 1-hot bus are '1'
-----------------------------------------------------------------------------
-- Begin architecture
----------------------------------------------------------------------------- begin
-------------------------------------------------------------------------------
-- Padded bus generation
------------------------------------------------------------------------------- pad_1hot_bus(0 to C_1HOT_BUS_SIZE-1) '0');
begin
OR_GENERATE: for j in 1 to 2**i generate
--------------------------------------------------------------------------------- ---- Here error occurs : ---- Error : or_bits is not an entity name
---------------------------------------------------------------------------------- BUS_OR: entity proc_common_v2_00_a.or_bits generic map ( C_NUM_BITS => PAD_1HOT_BUS_SIZE/2**(i+1), C_START_BIT => PAD_1HOT_BUS_SIZE/2**(i+1) + (j-1)*PAD_1HOT_BUS_SIZE/
2**i, C_BUS_SIZE => PAD_1HOT_BUS_SIZE ) port map ( In_Bus => pad_1hot_bus, Sig => temp_or(j-1), Or_out => temp_or(j) ); end generate OR_GENERATE;
Bus_enc(i)