Hi,
I am designing a simple ROM in VHDL and following is the code for it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the design(Implementation process).
When I use the test bench created by HDL bencher to see the results, in Modelsim, a behavioral simulation shows be proper results but a post translate simulation or anything beyond that like a Post Map or a Post place and route simulation show a U on all output pins and Modelsim gives me a number of warnings about "Unbound components" shown below..
Im stuck at this design phase and would appreciate any help from the VHDL gurus out there...Heres the code:-
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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity inrom is Port ( en : in std_logic; clk : in std_logic; dout : out std_logic_vector( 15 downto 0); valid : out std_logic; --valid data is present on output when 1 reset : in std_logic ); end inrom;
architecture rtl of inrom is
type array_rom is array (15 downto 0) of std_logic_vector( 15 downto
0); signal myarray : array_rom; signal valid_sig:std_logic; signal dout_sig : std_logic_vector(15 downto 0); signal clk2: std_logic;begin
myarray(0)