timing constraints

Hi,

I'm using a gigabit ethernet mac generated by coregen. Coregen generates a toplevel example and an .ucf file with some timing constraints, for instance:

############################################################ # PCS/PMA Clock period Constraints: please do not relax # ############################################################ NET brefclk_ibufg TNM_NET = brefclk; TIMESPEC TS_brefclk = PERIOD brefclk 16 ns HIGH 50 %;

This brefclk_ibufg signal is coming from a dcm that is in the generated toplevel. Now I have some wrappers around the "coregen toplevel" and assign the .ucf file to my own toplevel. But at that moment the signal brefclk_ibufg is not found anymore:

Annotating constraints to design from file "../../Gb_eth/vhdl_source/gb_eth_rtx.ucf" ... ERROR:NgdBuild:756 - Line 19 in '../../Gb_eth/vhdl_source/gb_eth_rtx.ucf': Could not find net(s) 'brefclk_ibufg' in the design. To suppress this error specify the correct net name or remove the constraint.

I tried something with paths, without success. Does anyone know how to fix this? Do I have to route the signal to my toplevel file or move the dcm part to my toplevel?

TIA, Frank

Reply to
Frank van Eijkelenburg
Loading thread data ...

Hi Frank, You need to find the name of the net after your synthesis process. So, run Translate, and open the Floorplanner that's listed alongside in the process window of navigator. Look for your DCM, and find the net name you want. Then edit you UCF file to match. I'm guessing that:- NET "*brefclk_ibufg" TNM_NET = brefclk; would work! Cheers, Syms.

Reply to
Symon

Symon,

thanks for the tip. I can not run the floorplanner, because the translate process is generating the error, but your suggestion about the name did work.

Frank

process

Then

Reply to
Frank van Eijkelenburg

Reply to
Symon

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.