Trouble using DCMs in EDK 8.2

I'm currently developing a design for the XUP development board. The development software is Xilinx EDk 8.2 The system requires several frequencies.

Power PC : 100 MHz PLB : 50 MHz

User IP : 50 MHz, 2.5 MHz

The EDK uses DCM_0 to divide the 100 MHz by 2. I use 2 cascaded DCMs to generate the 2.5 MHz (first divides by 2, second divides by 10). But when I want to generate the bitstream the following messages and errors occur:

INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not connected to an external port in this design. A new port 'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected to this signal. INFO:NgdBuild:889 - Pad net 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' is not connected to an external port in this design. A new port 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' has been added and is connected to this signal.

Applying constraints in "xup_morpheus5.ucf" to the design...

Checking timing specifications ... INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification "TS_sys_clk_pin", was traced into DCM instance "dcm_0/dcm_0/Using_Virtex.DCM_INST". The following new TNM groups and period specifications were generated at the DCM output(s): CLK2X: TS_dcm_0_dcm_0_CLK2X_BUF=PERIOD dcm_0_dcm_0_CLK2X_BUF TS_sys_clk_pin/2 HIGH 50% CLKDV: TS_dcm_0_dcm_0_CLKDV_BUF=PERIOD dcm_0_dcm_0_CLKDV_BUF TS_sys_clk_pin*2 HIGH 50% INFO:XdmHelpers:851 - TNM "dcm_0_dcm_0_CLKDV_BUF", used in period specification "TS_dcm_0_dcm_0_CLKDV_BUF", was traced into DCM instance "board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I /DCM_INST". The following new TNM groups and period specifications were generated at the DCM output(s): CLKDV: TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_ CLKDV_BUF=PERIOD board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_CLK DV_BUF TS_dcm_0_dcm_0_CLKDV_BUF*2 HIGH 50% INFO:XdmHelpers:851 - TNM "board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I _CLKDV_BUF", used in period specification "TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbi t_I_CLKDV_BUF", was traced into DCM instance "board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_2 _I/DCM_INST". The following new TNM groups and period specifications were generated at the DCM output(s): CLKDV: TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_ I_CLKDV_BUF=PERIOD board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_I_C LKDV_BUF TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_ CLKDV_BUF*10 HIGH 50%

ERROR:NgdBuild:455 - logical net 'plb_bram_if_cntlr_1_port_BRAM_Clk' has multiple driver(s): pin PAD on block plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_port_BR AM_Clk with type PAD, pin O on block dcm_0/dcm_0/Using_BUGF_for_CLKDV.CLKDV_BUFG_INST with type BUFG ERROR:NgdBuild:924 - input pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is driving non-buffer primitives: pin C on block reset_block/reset_block/core_cnt_en with type FD, pin C on block reset_block/reset_block/Bus_Struct_Reset_0 with type FD, pin C on block reset_block/reset_block/Rstc405resetchip with type FD, pin C on block reset_block/reset_block/Peripheral_Reset_0 with type FD, pin C on block reset_block/reset_block/Rstc405resetsys with type FD, pin C on block reset_block/reset_block/Core_Reset_Req_d3 with type FD, pin C on block reset_block/reset_block/CORE_RESET/q_int_0 with type FDRE, pin C on block reset_block/reset_block/CORE_RESET/q_int_1 with type FDRE, pin C on block reset_block/reset_block/CORE_RESET/q_int_2 with type FDRE, pin C on block reset_block/reset_block/CORE_RESET/q_int_3 with type FDRE, pin C on block reset_block/reset_block/SEQ/pr_dec_0 with type FDR, pin C on block reset_block/reset_block/SEQ/pr_dec_1 with type FDR, pin C on block reset_block/reset_block/SEQ/chip_dec_0 with type FDR, pin C on block reset_block/reset_block/SEQ/chip_dec_2 with type FD, pin C on block reset_block/reset_block/SEQ/pr_dec_2 with type FD, pin C on block reset_block/reset_block/SEQ/chip_dec_1 with type FDR, pin C on block reset_block/reset_block/SEQ/bsr_dec_0 with type FDR, pin C on block reset_block/reset_block/SEQ/bsr_dec_2 with type FD, pin C on block reset_block/reset_block/SEQ/seq_clr with type FDR, pin C on block reset_block/reset_block/SEQ/ris_edge with type FDR

ERROR:NgdBuild:455 - logical net 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' has multiple driver(s): pin O on block board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/ CLKDV_BUFG_INST with type BUFG, pin PAD on block board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1 with type PAD

ERROR:NgdBuild:924 - input pad net 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' is driving non-buffer primitives: pin O on block board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/ CLKDV_BUFG_INST with type BUFG

Does anybody know this problem. I did not apply any changes to the PLB_BRAM_IF_CNTL. Do I have to specify the new clock lines in one of the EDK files?

Thanks in advance Sebastian Goller

Reply to
Sebastian Goller
Loading thread data ...

TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_

board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_CLK

TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_

board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_I_C

TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_

It seems that you have connected more than one nets to the same output or inout port.

Reply to
Perry

I already checked the source code and the edif netlist (design_analyzer). Everything is okay. The point that confuses me the most is, that the error regarding plb_bram_if_cntlr_1_port_BRAM_Clk occurs when I use the DCM_0 in the EDK. If I use the same frequency for the PowerPC and the PLB there is no problem at all. Same thing with the two cascaded DCMs in the user IP. No signal has more than one driver. The simulation of the behavioral model and the structural model works fine. Is there anything I have to add to the .mhs or the .mpd or to another file? I have already tried to modify the .ucf-file. I added the following lines

Net "sys_clk_s" TNM_NET = "sys_clk_s"; TIMESPEC "TS_sys_clk_s" = PERIOD "sys_clk_s" "TS_sys_clk_pin"/2; Net "board1_unit0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1" TNM_NET = "clkdv_dcm1"; TIMESPEC "TS_clkdv_dcm1" = PERIOD "clkdv_dcm1" "TS_sys_clk_s"/2;

After restarting NGDBUILD the following error occurs:

INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not connected to an external port in this design. A new port 'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected to this signal. INFO:NgdBuild:889 - Pad net 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' is not connected to an external port in this design. A new port 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' has been added and is connected to this signal.

Applying constraints in "xup_morpheus5.ucf" to the design... INFO:NgdBuild:757 - Line 14 in 'xup_morpheus5.ucf': The constraint for NET 'sys_clk_s' is being attached to the equivalent NET 'plb_bram_if_cntlr_1_port_BRAM_Clk'. ERROR:NgdBuild:756 - Line 16 in 'xup_morpheus5.ucf': Could not find net(s) 'board1_unit0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' in the design. To suppress this error specify the correct net name or remove the constraint. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "xup_morpheus5.ucf".

What I do not understand is that NGDBUILD gives me an information about the signal "board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1" and five seconds later the signal can not be found in the design.

Reply to
Sebastian Goller

You set timing constraint for "board1_unit_0/board1_unit_0/ USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1", but you didnt specify a pin for it. Try to set a pin constraint for it.

Reply to
Perry

Thanks for your help. I have found out that I need to remove the IBUFGs of the DCMs generated by CoreGenerator. An IBUFG has to be connected to a pad, which is not the case in my design.So after

Reply to
Sebastian Goller

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