Timing constraints (again)

Hi all, What should I read to find out about timing constraints in detail? not just syntax but some theory. and how are the constrains interpreted? is the logic routed according to timing constraints? What if I use more than 90% of the available resources?

Also I am using an async fifo in my design. Is it necessary to use timing constraints for this?

Thanks in advance Subhasri

Reply to
Subhasri krishnan
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The best timing constraint document I have read is ftp://ftp.xilinx.com/pub/documentation/misc/timingcsts6i.pdf

187 pages of the stuff.


Reply to
Kunal Shenoy

If you are just begining, I would suggest going to the Constraints Guide. Help - Online Documentation - go to page 3 and Constraints Guide - then go to Timing Constraints Strategies - which is page 131 of 888 in my system.

I also think that "Understanding Setup and Hold Times" by Claude Gaschet Xilinx XL35-40.PDF is a nicely written article. If you can't find it on Google or at

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let me know.

Using an async fifo is what constraints are all about. You will have two "clock domains", probably one writting and one reading. That will mean at least four lines of UCF file code, two for each domain, sort of like this:

NET "clock1_in" TNM_NET = "clock1_in"; TIMESPEC "TS_clock1_in" = PERIOD "clock1_in" 20 ns HIGH 10; NET "clock2_in" TNM_NET = "clock2_in"; TIMESPEC "TS_clock2_in" = PERIOD "clock2_in" 5 ns HIGH 2.5;

Then you may want an OFFSET to address the setup time for incoming data:

OFFSET = IN 1 ns BEFORE "clock2_in";

This will move fabric registers toward the inputs.

Good luck,

Brad Smallridge brad at aivision.com

Reply to
Brad Smallridge

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