EDk and DCM

HI

I'm working on an microblaze project and i'm stuck at a problem with a dcm. i generated a new project with the wizard and the i added an additional dcm. i also have an instance of an SPI module in my design. i want to connect the clock_fx output of the dcm with the clock input of the spi module.

you can see my project : system.mhs http://193.170.52.132/xilinx/system.mhs system.ucf http://193.170.52.132/xilinx/system.ucf

here i connected the opb spi clock input: PORT OPB_Clk = dcm_spi_CLKFX

the dcm is set to generate 24MHz output

when i try to syntesize i get the timing error for the dcm_spi_CLKFX: http://193.170.52.132/xilinx/xflow.log (scroll almost all the way down)

when i connect the OPB_Clk to the normal clock line that feed the dcm and the rest of the curcuit it works fine.

could anybody help me or give me a hint here? thanks

Reply to
u_stadler
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I've never used opb_spi, but I believe the problem is that OPB_Clk for the entire bus must be that same. If you want to run spi at a slower speed you must use the C_OPB_SCK_RATIO parameter to divide the clock.

Alan Nishioka

Reply to
Alan Nishioka

I think I had the same problem when I added a second DCM to a project. The timing report quoted very large periods of negative slack. This is because the tools analyse paths between different clock domains. Look at the source and destination clocks in the verbose timing report.

I had taken the necessary precautions where signals passed between domains, and I did not want the tools to try and analyse them, so I added TIG (timing ignore group) constraints to my ucf file:

NET clk_foo TNM_NET = clk_grp1; NET clk_bar TNM_NET = clk_grp2; NET clk_xyz TNM_NET = clk_grp3; TIMESPEC TS_tig1 = FROM clk_grp1 TO clk_grp3 TIG; TIMESPEC TS_tig2 = FROM clk_grp2 TO clk_grp3 TIG; TIMESPEC TS_tig3 = FROM clk_grp3 TO clk_grp1 TIG; TIMESPEC TS_tig4 = FROM clk_grp3 TO clk_grp2 TIG;

There were 3 clock domains in my project. I did not need TIGs between grp1 and grp2 because there were no direct signal paths.

Reply to
Andrew Holme

hi

thanks for the answers.

well i changed my ucf file now to this :

## System level constraints Net sys_rst_pin TIG;

Net sys_clk_pin TNM_NET = sys_clk_pin; #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 19000 ps;

NET dcm_spi_CLKFX TNM_NET = clk_grp_spi;

TIMESPEC TS_tig1 = FROM sys_clk_pin TO clk_grp_spi TIG; TIMESPEC TS_tig2 = FROM clk_grp_spi TO sys_clk_pin TIG;

#TIMESPEC TS_spi_clk_pin = PERIOD clk_grp_spi 25000 ps; #NET dcm_spi_CLKFX TIG;

but when i try to run xflo i get the following error message:

Checking timing specifications ... WARNING:XdmHelpers:793 - The TNM "sys_clk_pin" drives the CLKIN pin of DCM "dcm_0/dcm_0/DCM_INST". This TNM cannot be traced through the DCM because it is not used exclusively by one PERIOD specification. This TNM is used in the following user groups and/or specifications: TS_tig1=FROM sys_clk_pin TO clk_grp_spi TIG TS_tig2=FROM clk_grp_spi TO sys_clk_pin TIG WARNING:XdmHelpers:625 - No instances driven from the following signals or pins are valid for inclusion in TNM group "sys_clk_pin". A TNM property on a pin or signal marks only the flip-flops, latches and/or RAMs which are directly or indirectly driven by that pin or signal. signal "sys_clk_pin" WARNING:XdmHelpers:644 - No appropriate elements were found for the TNM group "sys_clk_pin". This group has been removed from the design. ERROR:XdmHelpers:648 - The specification "TS_tig1" is invalid because its FROM group (sys_clk_pin) was removed. ERROR:XdmHelpers:648 - The specification "TS_tig2" is invalid because its TO group (sys_clk_pin) was removed.

what am i doing wrong? why is "sys_clk_pin" removed? thanks

Reply to
u_stadler

u snipped-for-privacy@yahoo.de schrieb:

what are you doing??

The OPB_SPI has __no__ SPI master clock input port !! the OPB_Clk must have default connection to system clock and the SPI clock is generated from it, but you can not feed the OPB_Clock of the OPB_SPI with some other clock.

its of course stupid that the OPB_SPI can only have SPI clock as 2n divided OPB clock but so it is

Antti

Reply to
Antti

oh... thanks a lot for pointing that out Antti!

so this means i can't have an spi output clock of 12 MHz? (because my obp clock is 50) is there any other way to do it?? i have seen that in edk 8.2 the only possible clock div for the spi is

  1. this means i can only get a max of 3.125 MHz for the spi clock? are there workarounds for that?

thanks urban

Reply to
u_stadler

u snipped-for-privacy@yahoo.de schrieb:

the min divide is less than 16, but i think there is some mess with documentation and/or parameter validation

divison factor below 16 is possible for sure, but you cant have arbitraty SPI clock, that also sure

Antti

Reply to
Antti

oh thats interesting. below 16 would work. what do you mean with an arbitraty SPI clock? generate a clock frequency with a dcm and connect the dcm output to an external fpga pin and use that as the spi clock?

thanks

Reply to
u_stadler

u snipped-for-privacy@yahoo.de schrieb:

I did mean that arbitrary clock is NOT possible with the OPB_SPI core

eg you would need to either modify it or develop your own core

Antti

Reply to
Antti

sorry. should read more carefully.

thanks

Antti schrieb:

Reply to
u_stadler

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