question: timing constraint for clock enable

Let's assume I have a global clock running at 80 MHz and a 2 bit counter running from this clock, which generates a 20 MHz clock enable signal.

Now I'm going to put a lot of combinatorial logic between two registers, which are clocked from the 80 MHz clock and enabled with the 20 MHz CE signal.

How can I constrain this design so that it is not being placed and routed for 80 MHz? Is there a way to apply any sort of timing constraint to the clock enable signal / net?

TIA, Stephan Flock

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Stephan Flock
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Stephan, There is something called a multi-cycle constraint that should help. Below is a link to help you get started in your search.

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Stephan, Xilinx? If so in your UCF file do this:- NET "enable" TNM_NET = "enable_FFS"; TIMESPEC TS6070 = FROM : enable_FFS TO enable_FFS : 50ns; A discription of this is in the contraints guide in the "TNM_NET" section. HTH, Syms.

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Thank you Newman and Syms,

TNM_NET and TIMESPEC FROM TO seems to be exactly what I was looking for.


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Stephan Flock

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