Hi.
In a SpartanIIe design I use an input signal as clock, although it does not enter the chip through a global clock pin. To do this, I instantiate an IBUF and a BUFG.
Now I want to put a timing constraint on the BUFG output. In the ISE5 timing constraints editor, the clock appears under a different name, whenever I change the design. It's called _n0063 or _n0067 etc.
Can I specify a name for the clock net somewhere in the VHDL code?
Here's the code I use (PBUS_CLK is the input signal, ICLK is the clock):
C1: IBUF port map (I => PBUS_CLK, O => PBUS_CLK_IBUF); C2: BUFG port map (I => not(PBUS_CLK_IBUF), O => ICLK);
Kind regards,
Marc