I'm generating a new design using an Altera Cyclone FPGA. But I think this issue may be applicable to all FPGAs. I have 8 identical modules that each have an 11 bit status register. The CPU (in this case a NIOS embedded on the same device) needs to read these status registers.
The question is what is the best (size first, speed second) configuration for these inputs? Can I use a tristate type construction and save interconnects to the CPU. Does this really save any routine resources and at what expense. In this design I can live with long delays on reading the status registers.
Any input would be appreciated.