Do you have a question? Post it now! No Registration Necessary
Subject
- Posted on
ISE 5.2 constraint file problem
- 09-03-2003
- David Lamb
September 3, 2003, 4:19 pm

Hi,
I have a vhdl project and I used a UCF file to assign the package pin to
each port in the design. This works fine. However, if I change my vhdl code
(let's say I remove an output port), I always get the following error when I
try to run the UCF editor:
ERROR:NgdBuild:756 - Line 3 in 'constraints.ucf': Could not find net(s)
'outputA' in the design. To suppress this error specify the correct net
name or remove the constraint.
It seems like the UCF doesn't update itself with the new design. I tried
everything and I always have to start with a new UCF each time. The removed
port doesn't exist in the Edit constraints (TEXT) because I didn't add any
constraint to it. I really don't see how to do it.
Thanks
David
I have a vhdl project and I used a UCF file to assign the package pin to
each port in the design. This works fine. However, if I change my vhdl code
(let's say I remove an output port), I always get the following error when I
try to run the UCF editor:
ERROR:NgdBuild:756 - Line 3 in 'constraints.ucf': Could not find net(s)
'outputA' in the design. To suppress this error specify the correct net
name or remove the constraint.
It seems like the UCF doesn't update itself with the new design. I tried
everything and I always have to start with a new UCF each time. The removed
port doesn't exist in the Edit constraints (TEXT) because I didn't add any
constraint to it. I really don't see how to do it.
Thanks
David

Re: ISE 5.2 constraint file problem

when
any
I use Aldec for a front end to Xilinx. This UCF editor is a major problem
for me always. The two don't communicate well with regards to the ucf, and
any changes that it may have. You can get into an endless loop where one
wants the other to fix it, but it can't because he wants him to fix it etc..
"You must run translate after modifying the ucf". So try and run translate
and it says the ucf has an error because you added things etc. Very
frustrating.
Site Timeline
- » New to FPGA, seeking advice
- — Next thread in » Field-Programmable Gate Arrays
-
- » MICROBLAZE: user core problem
- — Previous thread in » Field-Programmable Gate Arrays
-
- » Division Algorithms
- — Newest thread in » Field-Programmable Gate Arrays
-
- » WHO experts weigh in on COVID-19 vaccine dose interval
- — The site's Newest Thread. Posted in » Electronics Design
-
- » Dyrektywa o zakazie obrotu prekursorami materiał ów wybuchowych
- — The site's Last Updated Thread. Posted in » Electronics (Polish)
-