Prope timing constraint for this pin?

Hi.

I'm working on a V4 project, but I struggle with the timing constraints.

The design has one 125MHz oscillator. In an EDK submodule, this clock is divided to 62.5MHz for the bus clock (system generator did this for me). I use the 62.5MHz clock for many of my own modules, too (at the ISE level).

Until now, I only had one single timing constraint. I specified the

125MHz input as 8ns with 0.5ns jitter. I had the impression that the toolchain automatically detects that everything else is derived from it, and "does the right thing".

However, I noticed that there is a problem with an external chip. The chip is a kind of FIFO memory with asynchronous OE and synchronous RD pin (and corresponding CLKIN). It has a bi-directional databus.

In a clocked process (at 62.5MHz from the EDK submodule) I toggle CLKIN for the external chip (resulting in a 31.25MHz clock seen by it). In a similar clocked process, I set OE and RD as required for the bus protocol. I told ISE to register outputs directly in the IO- blocks, so I assume the external chip sees CLKIN, OE and RD change almost simultanously.

To read the FIFO databus in my design, I instantiate IOBUFs. The pin data is sampled in a clocked statemachine (again, at 62.5MHz). This happens one clock cycle after having updated the OE pin, ie after

16ns. The external chip is specified to output data 10.5ns after OE.

This works most of the time, but sometimes it does not. I think I need to put a timing constraint on the pins to make the flakey behaviour go away. I assume that the tools think that they have the full 16ns clock cycle for routing and logic from the I/O pin to the register. But in fact the external chip is eating 10.5ns of this budget, leaving only 5.5ns for the FPGA.

I figured that I have to tell this to the tools, somehow. So I read on timing constraints and found "pad to setup", which seemed to be the most appropriate one. However, this constraint expects me to specify a clock as well and I don't have that clock. Because the clock is not an external clock (it is generated within the EDK submodule), the constraint editor won't offer it for selection. It offers my external

125MHz, but not the 62.5MHz.

What is the proper way to define the timing constraint for my databus? Is "pad to setup" really what I should use, and if yes, how do I get ISE to offer the divided 62.5MHz clock in the timing constraint editor? And once I get 62.5MHz offered, what value do I have to enter for the constraint, 10.5ns (budget for external chip) or

5.5ns (budget for FPGA routing and logic)?

Kind regards, Marc

Reply to
jetmarc
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.