When compiling a design I receive the following message:
:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical timing constraint summary will appear in the map report. This summary will show a MINIMUM net delay for the paths. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual. For more information on TRCE, consult the Xilinx Development System Reference Guide "TRACE" chapter.
The problem however is that I receive no information WHICH SIGNAL PATH generates that problem, so I'm not able to redesign my core... The timing constraints are already the most liberal to be accepted by external hardware.
How to identify the path generating the problem? I can not run the timing analyzer, because the map fails.