IBUFG and BUFG +xilinx

Howdy Williams,

I believe the tools will usually do it for you - the exception that comes to mind is differential clocks.

BUFG is another name for a global buffer. Although most of the time you'd want it on a global buffer, the output of a DCM is not "already BUFG", nor would you always want it to be. Even if it does automaticly insert a BUFG in some situations, I rarely trust that it will every time.

Have fun,

Marc

If you manually insert BUFGs and IBUFGs, the tools will not try to insert another one, so put them in to make sure. Otherwise you can find that later on, when your design becomes more dense, your clock can suddenly be put onto longlines or even local routing.

-Jim

PS, I think your post belongs only on comp.arch.fpga, the others are for language specific questions.

Williams,

By default, an IBUFG & BUFG are instantiated, but if you specify something like:

wire dcmclkout; // synthesis attribute clock_signal of dcmclkout is true // synthesis attribute clock_buffer of dcmclkout is none

the synthesis tool will not issue a clock buffer placement.

i usually instantiate IBUFG & BUFG, for safety. hope this helps.

Vladislav

What if you route an IBUFG input pin to a regular BUF?...will the tools still treat it as global clock?

No, this net will be routed on local resources. The IBUFGs feed a routing box near the top center and bottom center of the chip, these have connections to the local resources (HEX lines, etc) and these get used. I accidentally ended up doing this once, saw the problem in FPGA editor, then fixed it. If you want to get a clock out of the FPGA, configure the output buffer as a DDR Flip Flop, tie D0 high, D1 low, give your clock to C0 and an inverted version to C1.

See XAPP462 for details, it's a very good document on the capabilities of the DCM.

-Jim