I am working with an EDK design that utilizes an MPMC2 core. There are several clocks associated with this core. All of the clocks are created using DCM's and inverters. I am failing timing b/c cross- clock domain paths are being analyzed and are failing.
My first question is: Should these paths be analyzed for this core? I didn't see any info in the documentation. I know the calibration routine/architecture is supposed to take care of finding the sweet spot to sample data so a TIG should apply for that logic. But I am not certain if every cross-domain path in the core is a TIG.
Second question: If all the paths are indeed TIG's, then is there an easy way to make the constraints? The only timing constraint currently implemented is the input clock to the FPGA that is fed to the DCM chain. Then all other clocks constraints are automatically determined by the tools. Is there a similar feature where I can tell the tools to apply TIG constraints to certain DCM-derived clock paths?