Hello,
I implemented a design which uses DCM in Virtex-II Pro XC2VP30-7. I have used ISE 9.2. for design implementation. In the constraint .ucf file, I put the timing constraint for DCM to be 10 ns. Then, I ran the simulation of my placed-and-routed design and I used the generated .VCD file as an input simulation file for XPower. The frequency of DCM clock in the simulation file was set to 50MHz (period of 20 ns). However, in the XPower advanced report I saw that the clock frequency was set to 100MHz, and according to that the dynamic power was almost two times higher than it is in the case when no timing constraint is applied. Hence, the tool ignored the frequency I set in the simulation file. I need the timing constraint to generate the design, but it seems that later on I can not simulate it with any frequency other than the one that was set as a timing constraint. Is there a way I can change this and simulate my design with the frequency I choose?
Thanks in advance.
Ruzica