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Re: TIG Constraint
- 08-25-2003
- Martin Euredjian
August 25, 2003, 8:47 pm


the
Using:
// synthesis attribute TIG of <net_name> is "TRUE";
makes the error go away. Is there a way to verify that the net is being
ignored for timing purposes? The log says:
Set user-defined property "TIG = TRUE" for signal <signal_name>.
Being that the constraints guide does not list "TRUE" as a valid value I'd
like verification that the constraint is truly doing something useful.
Thanks,
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
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Martin Euredjian
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Re: TIG Constraint
Sure, I could use multi-cycle in the UCF (or TIF, for that matter). For
maintainability (and reusability) purposes I wanted to include these and
other constraints with the HDL file.
maintainability (and reusability) purposes I wanted to include these and
other constraints with the HDL file.
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
We've slightly trimmed the long signature. Click to see the full one.
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