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[map error] unable to pack a IBUF into the IOB

hi

When exercising xapp290.pdf example, I met following error message during MAP stage.

---------------------------------------------------- ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "clock" (Pad Signal = clock) BUF symbol "clock_IBUF" (Output Signal = clock_IBUF) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "clock_IBUF" (LOC=BUFGMUX4S) Please correct the constraints accordingly.

----------------------------------------------------

Meanwhile, I found following Answer in Xilinx Answer browser

--------------------------------------------------- The GCLK IOs can only use IBUFGs, so the tool is unable to pack a IBUF into the IOB. To work around this issue, specify that the net use an IBUFG. This can be done by instantiating it in your code or adding a BUFFER_TYPE constraint to your code with the value set to IBUFG. The syntax for these can be found in the Software Manuals.

--------------------------------------------------

However, when I put the following attribute, still same error message appeared.

// synthesis attribute BUFFER_TYPE clock "ibufg";

Does anyone have any suggestion? Thankyou in advance.

Reply to
Pasacco
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Pasacco schrieb:

You are on the right path. It 'clock' is ffed into a GCLK pin, it must use a IBUFG!

Those damm attributes are case sensitive, even in VHDL (which is usually NOT case sensitive) use

// synthesis attribute BUFFER_TYPE clock "IBUFG";

instead. But if 'clock' is used a s a clock inside your code, the compiler will detect this automatically and insert an IBUFG. So no need for explicitly using the attribute.

Regards Falk

Reply to
Falk Brunner

Hi

When I remove following line in UCF file,

INST "clock_ibuf" LOC = "BUFGMUX4S" ;

there is no error encountered in the MAP stage.

But, in PAR stage, following error occurred.

-------------------------------------------------------- ERROR:DesignRules:576 - Netcheck: The signal clock_IBUF has a sigpin on the comp

Q1_12_OBUF that is not in the same route area as another sigpin of the same signal. This is not permited for Modules in partial reconfiguration mode unless the signal has the property IS_BUS_MACRO. ERROR:DesignRules:10 - Netcheck: The signal "clock_IBUF" is completely unrouted.

--------------------------------------------------------

I found Answer in Answer browser

------------------------------------------------------- This error occurs when signals attempt to route across a reconfigurable module boundary without going through a bus macro. Please ensure that any signal crossing the reconfigurable module goes through a bus macro.

-------------------------------------------------------

It is unclear for me what is wrong and why the tool tries to use "IBUG" instead of "IBUFG".

If someone gives any suggestion, it will be nice. Thankyou in advance

Reply to
Pasacco

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