Xilinx ISE 8.1i Trouble

The VHDL source and UCF file are at the bottom of this document.

The error that I'm getting is: NCD was not produced. All logic was removed from design. This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in the mapper.

I've got all my ports connected (see the UCF), and my logic seems right (it's just a sample from the Xilinx "Quick Start") ... what am I missing? I can get something simple working (like, OUTPUT(0)

Reply to
Alex
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Try

NET "COUNT_OUT[0]" LOC = "F12" ; NET "COUNT_OUT[1]" LOC = "E12" ; NET "COUNT_OUT[2]" LOC = "E11" ; NET "COUNT_OUT[3]" LOC = "F11" ;

-girmann

Alex wrote:

Reply to
girmann

Reply to
Alex

What are you using to synthesize your design?

If you are using XST (i.e. synthesis within ISE), make sure the "add I/O pads" option is checked in the GUI or passed on the command line. Otherwise the netlist created from synthesis will have no I/Os, and the mapper will throw away your design because it cannot affect the outside world...

Cheers,

-Ben-

Reply to
Ben Jones

Might I suggest you use use the numeric_std library? That works fine for me. From the par report file:

Device Utilization Summary:

Number of BUFGMUXs 1 out of 16 6% Number of External IOBs 6 out of 140 4% Number of LOCed IOBs 6 out of 6 100%

Number of SLICEs 3 out of 1408 1%

Using this file:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity ffff is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end ffff;

architecture Behavioral of ffff is signal count_int : unsigned(3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int

Reply to
Duane Clark

Yes, I am indeed using XST. Where is this "add I/O pads" option within ISE?

Thanks!

Alex McHale

Ben J>

Reply to
Alex

Process Properties for XST | Xilinx Specific Options | Add I/O Buffers (should be checked).

Cheers,

-Ben-

Reply to
Ben Jones

In that case, that did not solve the problem. That was already enabled.

Any other thoughts? This is a complete road block for me in development. I just don't understand why this thing won't work with anything more complicated than directly wiring the switch to the LED.

I can send a zip of my project to anyone willing to help. I'm using Xilinx 8.1i WebPACK, with the latest service pack.

Thank you.

Alex McHale

Ben J> > Yes, I am indeed using XST. Where is this "add I/O pads" option within

Reply to
Alex

Delving a bit deeper, I see that I am getting the following warnings before the final error. When I disable "Add I/O Buffers," I get these warnings on all of my lines. When it is enabled, I only get it for my CLOCK.

While I'm sure my net list is correct, this must be a symptom of the issue that's preventing my vhdl to load.

Any ideas?

WARNING:NgdBuild:483 - Attribute "LOC" on "CLOCK" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute. WARNING:NgdBuild:483 - Attribute "IOSTANDARD" on "CLOCK" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

Reply to
Alex

Get a vhdl simulator and learn to use it.

-- Mike Treseler

Reply to
Mike Treseler

Not that I don't appreciate your brilliant insight, but all of the above has simulated just fine. The problem is in actually implementing it. I'm having a software issue, somewhere, and the question is.. where.

Thanks, though. You're a real gentleman .

Mike Treseler wrote:

Reply to
Alex

Alex ( snipped-for-privacy@gmail.com) wrote: : Delving a bit deeper, I see that I am getting the following warnings : before the final error. When I disable "Add I/O Buffers," I get these : warnings on all of my lines. When it is enabled, I only get it for my : CLOCK.

: While I'm sure my net list is correct, this must be a symptom of the : issue that's preventing my vhdl to load.

: Any ideas?

: WARNING:NgdBuild:483 - Attribute "LOC" on "CLOCK" is on the wrong type : of : object. Please see the Constraints Guide for more information on : this : attribute.

Perhaps you might want ro refer to the Constraints Guied as mentioned in the warning? It might prove instructive.

Synchronous clocks are routed on dedicated clock nets, and if you're not brining the clock into the device on a dedicated clock input pin then things won't work as it is not possible to directly connect the "CLOCK" net to a non clock pin. You'll need to insert the correct buffer.

cds

: WARNING:NgdBuild:483 - Attribute "IOSTANDARD" on "CLOCK" is on the : wrong type of : object. Please see the Constraints Guide for more information on : this : attribute.

Reply to
c d saunter

Sorry, I missed that point. I'll try your code on ISE and quartus when I get to work.

-- Mike Treseler

Reply to
Mike Treseler

Hi Alex,

I can take a look at it if you send it to me.

/Mikhail

within

Reply to
MM

Try commenting out the very first line of your UCF file (add # symbol in the beginning of the line). It seems as the pin you chose is not a proper clock pin...

/Mikhail

Reply to
MM

This file:

formatting link

synthesizes fine with quartus 6.0 and ise8.1i using a clean project and default contraints.

formatting link

-- Mike Treseler

Device utilization summary:

--------------------------- Selected Device : 4vfx12sf363-12 Number of Slices: 3 out of 5472 0% Number of Slice Flip Flops: 4 out of 10944 0% Number of 4 input LUTs: 4 out of 10944 0% Number of bonded IOBs: 6 out of 240 2% Number of GCLKs: 1 out of 32 3%

--------------------------- Constraint | Requested| Actual | Autotimespec constraint for clock net | N/A | 1.190ns|

Reply to
Mike Treseler

I snagged a different computer, installed WebPACK, the service packs, and tried again. It worked. It would appear that something is "broken" in my install on my workstation.

Now to figure out how to program the flash so that the circuit "sticks" between power cycles...

Thanks for looking. I appreciate it.

Mike Treseler wrote:

Reply to
Alex

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