The VHDL source and UCF file are at the bottom of this document.
The error that I'm getting is: NCD was not produced. All logic was removed from design. This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in the mapper.
I've got all my ports connected (see the UCF), and my logic seems right (it's just a sample from the Xilinx "Quick Start") ... what am I missing? I can get something simple working (like, OUTPUT(0)