Hi,
I'm trying to create a design that uses a LUT to control routing on a Virtex-II Pro. It's pretty easy to create the LUT in VHDL and feed it into a MUX to select the appropriate output based on the values in the LUT. I'm trying to use this in a partial reconfiguration design so that I can change the values in the LUT with a partial bitstream to change the routing. My problem is that the design is optimized and broken up in to multiple LUTs making it hard to determine what needs to be changed.
Is there any way to force the LUT to be left as a primitive and implement the equations (or initial value) that I set? I would also like to be able to force the LUT to be in known location so that I can find it easily in the NCD file. I've seen plenty of documentation staying this can be done, I can't find any exampled. I believe I can use an RLOC but I'm not sure where the RLOC constraint should be placed.
Thanks for your help,
David
Here's what I know so far:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all;
entity lut_mod is Port ( SW_0 : in STD_LOGIC; --just some simple inputs and SW_1 : in STD_LOGIC; -- outputs for testing SW_3 : in STD_LOGIC; LED_0 : out STD_LOGIC; LED_2 : out STD_LOGIC; LED_3 : out STD_LOGIC); end lut_mod;
architecture Behavioral of lut_mod is
signal LUT_to_MUX : STD_LOGIC;
begin
LED_3 LUT_to_MUX, -- LUT local output I0 => SW_3, -- LUT input I1 => SW_3, -- LUT input I2 => SW_3, -- LUT input I3 => SW_3 -- LUT input );
MUXF5_inst : MUXF5 port map ( O => LED_0, -- Output of MUX to general routing I0 => SW_0, -- Input I1 => SW_1, -- Input S => LUT_to_MUX -- Input select to MUX );
end Behavioral;