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Re: Enhancing PAR with FPGA floorplanners

As far as cost goes, it again comes down to what you are trying to achieve. Many times, the cost of the tools could be justified easily by showing the savings - for example, saving a speedgrade (use a slower speedgrade part) by the use of physical synthesis has a great impact on the total cost of your board.

Using placement constraints is okay if you are trying to meet timing on certain small sections of the designs AND you know if these are going to be the bottleneck. It is not feasible to do this if you have a big design that is using 90+% of the slices/LEs etc.

As FPGAs are getting bigger and can accomodate complex designs, there are newer physical synthesis tools in the market that have different approaches to solving the timing closure issue. It is definitely worthwhile to check them out.

IMHO these tools are very expensive and for my needs I am better with > placement constraints by hand then using these tools. This gives me even > better control and saves me time and money. But your needs may be > different. To be honest I don't see the benefit of e.g. Amplify which > would be worth the money. > > BR Chris > > > Alfredo wrote: > > > Thanks Neeraj, I have some notion of the benefits of these tools but I

do not

> fully understand how to differentiate them and how to choose one for a

specific

> task: which one is better for IP immersion, which one help manage better

for

> stitching blocs at the top level (modular design), which one interfaces

better

> with STA tools for timing closure, ... > > I think I'll need to run some testbenches to get a good grasp on these

tools and

> how to better use them. > > > > Does anyone have a book or documetation that I can read to learn more

about this

> subject? > > > > The only documentation I have now is what the vendors are providing. > > > > Thanks, > > > > *** > > Alfredo. > > > > > >>The Physical synthesis and SVP tools from 3rd parties are not just mere > >>Floorplanners. In a nutshell, Amplify and Precision Physical do

something

>>called "Placement Aware Synthesis", which is the most important thing to

do

>>to bring down the routing delays...whereas SVP tools like the one from

Hier

>>help provide final representation of the PLD design early in the design > >>stage. > >> > >>Floorplanning is just one of the many features built into these tools, > >>though an important one, to help achieve performance goals and reducing

the

>>compile time of the design by working closely with the P&R tools... > >> > >>Feel free to correct me if I am wrong... > >> > >>--Neeraj > >> > >> > >> > >> > >> > >> > >> > >> > >> > >> > >>>Hi, > >>>physical synthesis tools for FPGAs are being introduced by a few

vendors.

>> > >>Have > >> > >>>you read, evaluated or seen a presentation about these tools: > >>>Synplicity's Amplify: > >> > >>
formatting link
> >> > >>>Mentor's Precision:
formatting link
> >>>Hier Design's Plan Ahead:
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> >>> > >>>Do you have any thoughts about what you would be looking for in an FPGA > >>>floorplanner from a 3rd party (not the FPGA manufacturer)? > >>> > >>>Do you use Altera's or Xilinx floorplanner now? > >>> > >>>Thanks for you input, > >>> > >>>*** > >>>Alfredo. > >>> > >>> > >> > >> > > > > >
Reply to
Anil Khanna
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in

Ray's impressive designs are mostly regular structures, mostly data path. Placement in the bottom levels of code works well for such designs. When the critical paths are in complex control logic, such placement isn't a realistic alternative. Other techniques are more useful. FPGA designs are not all the same sorts of things. Different requirements lead to different usages of the parts and the tools.

--
Phil Hays
Reply to
Phil Hays

However, the complex-control-logic hairballs are what simulated annealing and related FPGA placement algorithms are designed to do best. A common (and effective) technique is to hand-place the regular datapath, and then let the placement tool arrange the control logic around the periphery.

--
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Reply to
Nicholas C. Weaver

How good is the current software?

Many years ago, I could, do a manual placement and automatic routing if far less time than the P&R tools took to do the whole job.

My "complex-control-logic hairballs" were generally pretty simple, mostly one-hot state machines. Maybe some pipelining to help. (They probably have to be simple if you are going to co-exist with a well planned data path.)

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Reply to
Hal Murray

Ray, What I have in mind is mid complexity designs that would benefit from some sort of automated flow to produce a better placement to fit into smaller or lower speed grade devices, as the vendors promise.

I understand that most high end designers will be doing floorplanning and constraining themselves, using on other tools, like formal verification, as they make progress.

But what I would like to know is what are the features to look for in a 3rd party floorplanner to make it worth it. If someone with average design experience, wanted to use one of this tools to stitch IP/blocs or to make modifications to other's designs (for an ECO, for example) what should I be looking for?

I have also looked at hierarchical methodologies, but it only works if implemented form the start. My testcases are large flat design that I've hacked. I've found it difficult to partition these designs and make the changes to the constraints to still meet timing. Most of these design had very narrow timing margins and/or were almost full. For me, this is were one of these tool might help. But I would appreciate input form this newsgroup.

Cheers,

*** Alfredo.

in

Reply to
Alfredo

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