I've been performing post-map static timing analysis and have noticed that my TIG UCF constraint is being ignored for some reason. Here is what I have:
## TIG NET "ctrl1_clr" TNM_NET = "TN_ctrl_clr"; NET "ctrl2_clr" TNM_NET = "TN_ctrl_clr"; NET "sync_drpp_clr_inst/sync_r2" TNM_NET = "TN_sync_drpp_clr"; NET "sync_drpp_clr_inst/sync_r2" TNM_NET = "TN_sync_drpp_clr"; TIMESPEC "TS_TIG_clr2synch" = FROM "TN_ctrl_clr" TO "TN_sync_drpp_clr" TIG;
The first two nets listed are assigned to a timing name belonging to paths that are asychronous to another clock. This clock drives registered ports of an instance (synchronization circuit) with port name sync_r2(1:0). Normally I would edit the UCF manually, but it absorbed some of the signal names, so instead I used the constraint tool to generate the above.
When I run timing I get the following:
WARNING:Timing:3223 - Timing constraint PATH "TS_TIG_clr2synch_path" TIG; ignored during timing analysis.
Here is one of the timing errors from the post-map static timing analyzer:
Timing constraint: TS_adc_clk_dcm_clkfx = PERIOD TIMEGRP "adc_clk_dcm_clkfx" TS_adc_clk / 0.7 HIGH 50%;
278920 items analyzed, 4 timing errors detected. (4 setup errors, 0 hold errors) Minimum period is 8.415ns.-------------------------------------------------------------------------------- Slack: -0.270ns (requirement - (data path - clock path skew + uncertainty)) Source: ctrl2_ins/curr_st_FFd1 (FF) Destination: sync_drpp_clr_inst/sync_r1_1 (FF) Requirement: 0.571ns Data Path Delay: 0.590ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: adc_clk_dcm_clk0_bufg rising at 28.000ns Destination Clock: adc_clk_dcm_clkfx_bufg rising at 28.571ns Clock Uncertainty: 0.251ns Timing Improvement Wizard Data Path: ctrl2_ins/curr_st_FFd1 to sync_drpp_clr_inst/sync_r1_1 Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tcko 0.291 ctrl2_ins/curr_st_FFd1 net (fanout=22) e 0.100 ctrl2_ins/curr_st_FFd1 Tfck 0.199 ctrl2_ins/curr_st_Out11 sync_drpp_clr_inst/sync_r1_1 ---------------------------- --------------------------- Total 0.590ns (0.490ns logic, 0.100ns route) (83.1% logic, 16.9% route)
Why is ISE ignoring my constraint? How am I supposed to know what my true worst path is if I can't eliminate this timing error?
Thanks,
-Brandon