I am implementing a direct digital frequency synthesizer in FPGA. It follows the equation
Fo = N * Fs / (2^M)
The implementastion is done by an M-bit phase accumulator. My question is: if 2^M cannot be divided by N, should the accumulator be cleared to zero when wrapping around?
The VHDL code for automatical wrap-around is:
process(clk, reset) begin if reset='1' then q'0'); elsif rising_edge(clk) then q tmp) then --reach 2^M-1 and wrap around q '0') else q