1. Home
  2. Field-Programmable Gate Arrays
  3. Period constraint

Period constraint

I am using DCM in VirtexII device. I feed 40 MHz clock to CLKIN and use CLK2X output (80Mhz) and CLKDV output (2.5MHz), so these clocks should be in phase. Can I feed output from flip/flop clocked by CLKDV directly to FF clocked by CLK2X without additional constraints except of PERIOD for CLKIN?

The PERIOD c "A clock period specification checks timing between all synchronous elements within the clock domain as defined in the destination element group. The group may contain paths that pass between clock domains if the clocks are defined as a function of one or the other."

Also examples show that it is possible to specify phase shift between clock and clock derived from this base clock. I think just to check path between two created in this way clock domains.

So, I think this path is checked, but I'm looking for some confirmation.

-- RobertP

Reply to
RobertP
Loading thread data ...

I am not certain, but I think the above text is saying that if you specify the derived clocks in terms of the starting clock, then the tool will check paths between the clock domains. This means you should say the period of CLKIN is 25 ns and the period of CLK2X is half of this and the period of CLKDV is 16 x this value.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.