Xilinx timing constraint problem

Nov 30, 2005 2 Replies
D

Dear all,



I place a timing constraint on a pair of registers (from, to) either side of some logic. After I run the ISE 6.3 toolchain, I look at the actual delays for the constraint in Timing Analyzer.



The constraint seems to have been applied from the source register which I specified as my destination, to a register or pad elsewhere in the design. The constraint is applied to logic other than specified.



Any suggestions?



Cheers,



Dave.


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R

Can you check the PCF to see if the FROM TO still references the correct register pair?

Russ

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D

Yes - FROM, TO is correct. The constraints are still being applied incorrectly FROM my specified TO group, going to some arbitrary destination. Not sure what's up.

Thanks,

Dave.

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