Xilinx constraining : differential clocks and other details

Hi,

For the first time, I'm working with differential clock inputs on the FPGA and I'd like to know how to properly constrain them.

Currently what I put in my ucf is (for a clkin clock with a 200 MHz frequency) :

TIMESPEC "TS_clkin" = PERIOD "clkin" 200 MHz HIGH 50%;

NET "clkin_p" TNM_NET = "clkin"; NET "clkin_n" TNM_NET = "clkin";

Is this correct ? Or should I define two timespec with an offset of half a period, or just constraint the clkin_p ?

I also have two others questions :

  • How to specify a maximum skew between multiple signals and also an offset in/out compared to a clk output. (i/e I output a clock using DDR FF and I want the related signals to be for example 1 to 2 ns after that clock).
  • Finally, in my ucf I put lines like

NET "leds" IOSTANDARD=LVCMOS33 | SLEW=SLOW | DRIVE=24;

but I get *tons* of warning about putting the IOSTANDARD and SLEW and DRIVE attribute on the "wrong type of object". What's the problem here ?

Thanks,

Sylvain

Reply to
Sylvain Munaut
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Just constrain the clkin_p. The differential receiver acts like a single input.

Usually this means that the tools did not interpret these nets to be the IO Pad net. Perhaps they are generated internally in a slice and then routed to an output buffer, where the tools have a different internal name for the pad net like leds_IOBUF or something similar. If these are outputs from your top level module, make sure that you tell the synthesizer to add IO buffers when you synthesize.

Reply to
Gabor

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