Pc and xcv200e doesn't talk,not exactly the right cable maybe..

I'm still here thanks to this newsgroup i finally built a cable III that works fine with cpld's like xc95144xl(3,3V),i can recognize it ,readback,erase,blank check and write. Then i dared to connect it with a (scraped as ever) fpga,a virtex xcv200e but the boundary scan chain does not see it at all.

what i did was this :

i built a level shifter for the TDO,because the cable is not expected to work with such low levels,this 2 bjt level shifter works fine even with a 4 mhz square wave,and i think this is faster than any signal could ever move through the parallel port(is it true?)

i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not easy to test it (soldering wires on a bga is even worse ...)but it looks that it should be enough for the core,correct???or i need to

i connected in 2 points the 3.3VCCO(B12 and A13) and the ground in 3 points(A1,J1,N12)

i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level amplifier)

I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same result.....

I left M0 and M2 open,and they are high,M1 tied to ground,this for choosing boundary scan mode

using the debug chain utility i verified that the signals are working

Thank you to everyone in the group that will help me or just will read this

Diego

Reply to
blisca
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Xilinx's Virtex-E datasheet (DS022-2 (v2.8) January 16, 2006), "Boundary Scan" section states:

"The JTAG input pins (TDI, TMS, TCK) do not have a VCCO requirement and operate with either 2.5 V or 3.3 V input signalling levels. The output pin (TDO) is sourced from the VCCO in bank 2, and for proper operation of LVTTL 3.3 V levels, the bank should be supplied with 3.3 V. "

So, it doesn't look like you need 1.8v JTAG circuitry.

HTH

-Dave Pollum

Reply to
Dave Pollum

thank you for helping me ok,i admit that i did'nt read it ,jumping to soon to the chapter "boundary scan mode"..........but......being a newbie,and feeding the xcv200e through wires,how can i identify the bank2 VCCO?i mean where are these VCCO pins ?

4

not

choosing

this

Reply to
blisca

Diego; The Xilinx web site contains lots of dcumentation for their chips. Table 6 in DS022-4.PDF, lists the XCV200E's pinouts for the PQ240 package. This is only package that looks like it could be used by a hobbiest. All of the other packages are BGA. Anyway, in DS022-4.PDF

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page 10 shows the pin numbers for the chip's banks. VCCO for bank 2 is on pins 176 and 165.

HTH

-Dave Pollum

Reply to
Dave Pollum

"boundary

through

?
Reply to
blisca

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