Help with Xilinx i/o constracint for ps/2 port

Jan 30, 2007 1 Replies
F

I am designing a PS2 interface for a board with Xilinx Spartan-3 device. The clock and data signals of the PS2 port are bi-directional and use open-collector circuit. On the board, there is a serial resistor between an FPGA pin and PS2 port. The following constraint is used in ucf file:



NET "ps2_clock" LOC = "..." | IOSTANDARD = LVCMOS33 | SLEW = SLOW | PULLUP;



Can anyone advice me whether it is ok? Can the "PULLUP" option be used to emulate the pull-up resistor in a open-collector circuit?



Thanks in advance.



S. C.



Vote
Twitter Facebook LinkedIn
A

The FPGA pull-ups are pretty weak, as they're basically intended to keep CMOS inputs at a known state. This means that the pull-up is slow. As long as you can tolerate that, you'll be OK. But the bad news is that you don't really know how weak they are. A proper pull- up resistor is a good thing.

-a

Vote
Twitter Facebook LinkedIn

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required