Hi,
I have a fairly simple Spartan-3 design which essentially implements an interface to an external MCU and it works fine. I need to interface to a 2nd data bus which is asynchronous to the main (MCU) clock. I want to multiply the main clock by 4 to implement a 2-stage FF synchroniser & data latching arrangement. I've incorporated the frequency synthesiser part of a DCM using core generator and I now get the following error (using ISE 8.2) :
ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed.
If I remove all pad constraints I no longer get this error. I've tracked the problem down to adding 1 or more signals to pins in bank 6. The summary report for the bank assignments is as follows:
Bank 0 has 10 pads, 9 (90%) are utilized. Bank 1 has 9 pads, 9 (100%) are utilized. Bank 2 has 14 pads, 14 (100%) are utilized. Bank 3 has 15 pads, 12 (80%) are utilized. Bank 4 has 11 pads, 2 (18%) are utilized. Bank 5 has 9 pads, 7 (77%) are utilized. Bank 6 has 14 pads, 1 (7%) are utilized.