problem with IO in EDK 8.1

M

Mich 20 years ago

Hi

I want to use a networkmodule of Digilent and I downloaded a VHDL file from there website. =>

formatting link

This works fine if I use it als a project at ISE 8.1. When I want to use it as part of an IP under EDK 8.1 it doesn't work.

I have made an IP with the create/inport wizard and I past the code in the User_Logic.vhdl file. I also adjust the vhdl file of the NET_IP.

I have placed this at the PMD file of the IP PORT pdb = "", DIR = INOUT, VEC = [7:0], THREE_STATE = FALSE, IOB_STATE = BUF PORT astb = "", DIR = I PORT dstb = "", DIR =I PORT pwr = "", DIR = I PORT pwait = "", DIR = O PORT leds = "", DIR = O, VEC = [0:3] and I made these signals external

then I placed this at the ucf file ## NET_IP NET NET_IP_0_pdb LOC = "R8"; NET NET_IP_0_pdb LOC = "R7"; NET NET_IP_0_pdb LOC = "P5"; NET NET_IP_0_pdb LOC = "P4"; NET NET_IP_0_pdb LOC = "R2"; NET NET_IP_0_pdb LOC = "T2"; NET NET_IP_0_pdb LOC = "R6"; NET NET_IP_0_pdb LOC = "R5"; NET NET_IP_0_pdb IOSTANDARD = LVTTL; NET NET_IP_0_pdb IOSTANDARD = LVTTL; NET NET_IP_0_pdb IOSTANDARD = LVTTL; NET NET_IP_0_pdb IOSTANDARD = LVTTL; NET NET_IP_0_pdb IOSTANDARD = LVTTL; NET NET_IP_0_pdb IOSTANDARD = LVTTL; NET NET_IP_0_pdb IOSTANDARD = LVTTL; NET NET_IP_0_pdb IOSTANDARD = LVTTL;

NET NET_IP_0_astb_pin LOC = "R4"; NET NET_IP_0_dstb_pin LOC = "R3"; NET NET_IP_0_pwr_pin LOC = "U1"; NET NET_IP_0_pwait_pin LOC = "V1";

NET NET_IP_0_astb_pin IOSTANDARD = LVTTL; NET NET_IP_0_dstb_pin IOSTANDARD = LVTTL; NET NET_IP_0_pwr_pin IOSTANDARD = LVTTL; NET NET_IP_0_pwait_pin IOSTANDARD = LVTTL;

NET NET_IP_0_leds_pin LOC = "AC4"; NET NET_IP_0_leds_pin LOC = "AC3"; NET NET_IP_0_leds_pin LOC = "AA6"; NET NET_IP_0_leds_pin LOC = "AA5";

NET NET_IP_0_leds_pin IOSTANDARD = LVTTL; NET NET_IP_0_leds_pin IOSTANDARD = LVTTL; NET NET_IP_0_leds_pin IOSTANDARD = LVTTL; NET NET_IP_0_leds_pin IOSTANDARD = LVTTL;

NET NET_IP_0_leds_pin DRIVE = 12; NET NET_IP_0_leds_pin DRIVE = 12; NET NET_IP_0_leds_pin DRIVE = 12; NET NET_IP_0_leds_pin DRIVE = 12;

NET NET_IP_0_leds_pin SLEW = SLOW; NET NET_IP_0_leds_pin SLEW = SLOW; NET NET_IP_0_leds_pin SLEW = SLOW; NET NET_IP_0_leds_pin SLEW = SLOW;

for some reason the pins of pdb (who are INOUT) are always 1 and never changes

Can someone please tell me what I 'm doing wrong?

Greets Michiel

Vote

M

Marco T. 20 years ago

I'm not sure but to implement a INOUT, I think you should use a tri-state buffer.

Marco

Vote

M

Mich 20 years ago

And how do I use a tri-state buffer???

Michiel

Vote

G

Guru 20 years ago

Hi Michiel,

To correctly use a tristate you need 3 ports in your peripheral design (VHDL) for a single port ("port") in MPD and UCF file: port_I port Input port_O port Output port_T port Toggle (low (0) enables you to write to tristate)

and in MPD: PORT port = "", DIR = INOUT, ENABLE=SINGLE, THREE_STATE=TRUE

in UCF: NET port LOC = xx;

I hope this helps.

Guru

Vote

M

Mich 20 years ago

Hi

I have test it and got this error ERROR:MDT - test_I (IO_0) - D:\Thesis\Test\XPS_versie8\IO\system.mhs line 358 - port is driven by a sourceless connector

this is what I have done first I added this in the vhdl test_I : in std_logic_vector (7 downto 0); test_O : out std_logic_vector (7 downto 0); test_T : out std_logic_vector (7 downto 0); and this s_test

Vote

G

Guru 20 years ago

Hi Mitch

Mich wrote:

ERROR: ENABLE=MULTI !!!!!!! and maybe endianicity [0:7]

As an example take a look at OPB_DDR MPD: PORT DDR_DQS = "", DIR = IO, VEC = [0:((C_DDR_DWIDTH/8)-1)], THREE_STATE = TRUE, ENABLE = MULTI, PERMIT = BASE_USER, DESC = 'DDR Data Strobe', IO_IF = ddr_0, IO_IS = data_strobe

DELETE THIS PART!!

UCF Seems fine, but only for ONE test pin, for multiple pins look at the example:

NET "gmii_txd" LOC = "M4"; NET "gmii_txd" LOC = "N4"; NET "gmii_txd" LOC = "L1"; NET "gmii_txd" LOC = "M1"; NET "gmii_txd" LOC = "P2"; NET "gmii_txd" LOC = "N5"; NET "gmii_txd" LOC = "P4"; NET "gmii_txd" LOC = "P5";

Cheers,

Guru

Vote

problem with IO in EDK 8.1

Join the Discussion

Didn't find your answer?