Hi, We are currently designing a Xilinx Spartan-3 FPGA based tool that needs to communicate with a daughter card. Multiple variations of daughtercard exist, each of which have a different IO voltage ( 1.5 to 3.3v)
As we dont know what voltage the FPGA IO bank is going to operate, (as daughtercard will be hot-plugged, so we may remove a 1.5V daughtercard and replace it with 1.8v one) the daughtercards are going to power the VCCO of FPGA (1.5 to 3.3v). The daughtercards are connected using 2 ft ribbon cable. so we would like to be able to tinker with the slew rate and drive strengths too. (that narrows me down to LVCMOS and LVTTL)
Only one daughtercard will be plugged in at a time, so i am not trying to use 2 IOSTANDARDs at the same time.
My question is, 1) In the UCF file, what IOSTANDARD should i set for the pins ? will it be ok if i select LVCMOS15 and expect that the IOs will work fine even at applied VCCO of 3.3v ? (setting the pin to LVCMOS33 may not go down well for 1.5v daughtercard ... ?)
2) how are the VOH/VOL values of the (input section of) FPGA pins related to VCCO actually applied and IOSTANDARD selected in the UCF ? My assumption is that the VOH/VOL are a percentage of VCCO actually applied to the VCCO pin. IOSTANDARD is just used by place-n-route tool to ensure that user does not place incompatible IOs in same bank.
any pointers that lead to answers are also fine.
meanwhile, i have already gone through the following before posting here. 1) xilinx ug331.pdf, "using IO resources" chapter, page-352, contains a table. in the IOSTD vs VCCO table, for the entry LVCMOS25 vs VCCO of 1.8v there is a '-' (which means, undefined). for Spartan 3A/AN, VCCO of 1.8 acts as input for LVCMOS25.
2) This comes surprisingly close to my problem.
Thanks
-mp