Xilinx ISE question

Hi, all,

Another one that's probably covered somewhere in the docs, but that I can't find there, and a bit of googling has come up with zilch.

I'm trying to get ISE 14.6 to assign CPLD pins in some vaguely rational way, e.g. not scattering wires in the same bus all over the place.

I ran the Lock Pins utility, which generated a UCF file with the right syntax. I then edited the pin placements to suit, and recompiled. The pins were different from before, but still nothing like mine, and no errors or warnings generated.

The floor plan generator doesn't seem to work properly, at least with this device. Double clicking on "Floorplan IO - Pre-Synthesis" brings up a dialogue box that asks to make a new UCF file, but after getting permission, the floor plan editor never comes up.

(OS is 64-bit Linux, CentOS 6.5, which is one they claim to support.)

Any wisdom? If this doesn't sound normal, I'll take it up with Xilinx, but hopefully somebody round here can help, because I'm up to my eyeballs in work at the moment.

Thanks

Phil Hobbs

============

// UCF file for BoxcarLockIn in XC9572XL-10PC44C (44 pin PLCC) #PINLOCK_BEGIN

#Wed Apr 16 16:32:05 2014

NET "Clock" LOC =" S:PIN=5"; NET "Go" LOC =" S:PIN=1"; NET "CW" LOC =" S:PIN=2"; NET "Rst" LOC =" S:PIN=3"; NET "TermCount" LOC =" S:PIN=6"; NET "TermCount" LOC =" S:PIN=7"; NET "TermCount" LOC =" S:PIN=9"; NET "TermCount" LOC =" S:PIN=9"; NET "LED" LOC =" S:PIN=33"; NET "Switch" LOC =" S:PIN=24"; NET "Switch" LOC =" S:PIN=25"; NET "Switch" LOC =" S:PIN=26"; NET "Switch" LOC =" S:PIN=27"; NET "Sample" LOC =" S:PIN=43"; NET "DataReady" LOC =" S:PIN=28"; NET "TermCount" LOC =" S:PIN=11"; NET "TermCount" LOC =" S:PIN=12"; NET "TermCount" LOC =" S:PIN=13"; NET "TermCount" LOC =" S:PIN=14";

#PINLOCK_END

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs
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If you even get into a situation where you'd like someone else to do the FPGA grunt work, I know a guy. We negotiate Visio block diagrams, and he battles the tools for me.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Gigantic huge disclaimer: I have never used this software.

Maybe remove this timestamp, or change it to a // comment?

These two nets are on the same pin. Maybe this is causing it to ignore all of your assignments?

You might also try changing the syntax a little. Programs that weren't born on Unix are usually horrible about parsing text files; they tend to have undocumented assumptions about whitespace or which column things are in. You might try this first

NET "LED" LOC=" S:PIN=33";

and then this

NET "LED" LOC="S:PIN=33";

or even

NET "LED" LOC "S:PIN=33";

to see if it helps. Change spaces to tabs (or vice versa), and so on.

Matt Roberds

Reply to
mroberds

Den onsdag den 16. april 2014 23.08.00 UTC+2 skrev Phil Hobbs:

the newest ISE I have installed here is 14.1 doesn't look like any ucf file I've ever used

normally the syntax is like this:

NET "Clock" LOC ="P5"; NET "Go" LOC ="P1";

-Lasse

Reply to
Lasse Langwadt Christensen

.....

...

Phil,

That syntax looks unusual. This is one for a CPLD I did:

# Pin definitions - Beeblebrox CPLD

# Bank 1 - 3.3V NET "CUM_GPIO" LOC = "39" | IOSTANDARD=LVCMOS33; NET "DBG_0" LOC = "40" | IOSTANDARD=LVCMOS33; NET "DBG_1" LOC = "41" | IOSTANDARD=LVCMOS33; ... NET "MODE" LOC = "32" | IOSTANDARD=LVCMOS18;

The pin number is just a number in quotes. The other (optional) part is to define the type of I/O.

kevin

Reply to
kevin93

You have to tell it to USE the UCF file. It will open a browse window where you can navigate to the UCF file. I think you can also add the ucf file to the design, and it will automatically recognize the UCF ending and do the above.

Jon

Reply to
Jon Elson

Thanks, I'll try that. The above syntax was created by the Lock Pins function, which also doesn't do anything except hack up the UCF file that then gets ignored.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

yes just add a file to the project with extension ucf, don't know if you have to call it the same as to the to module file but I've always done that since then it picks it up by default if you run the tools on a command line

-Lasse

Reply to
Lasse Langwadt Christensen

Did that. I also had to install some compatibility libraries, so it may be that some component doesn't run because it can't find some obscure libfoobar.so.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

If you can find the binary for the component, you can use the 'ldd' command to see 1) what libraries it wants and 2) how the loader on your system is going to satisfy those. If there are any "not found" entries, you should investigate. The output looks approximately like this:

$ ldd /usr/bin/xilinx-foo libc.so.6 => /lib/x86_64-linux-gnu/libc.so.6 (0x00007f0cadee0000) libpthread.so.0 => /lib/x86_64-linux-gnu/libpthread.so.0 (0x00007f0cadabf000) libxilinx-weird-stuff.0 => not found

The usual fixes are to either install more standard libraries, or to put all the weird libraries in a known location, put the path to that location in /etc/ld.so.conf , and then run ldconfig as root.

For command-line stuff, I find that if there is a missing library, the execution tends to fail right away; the loader doesn't even bother trying to run the program. On the other hand, a GUI (or script) might be trying to run various binaries, and not checking to see if they actually ran or not.

Matt Roberds

Reply to
mroberds

Thanks. This is a little 72-macrocell gizmo to run a combination lock-in and boxcar. The reason I'm doing it with a CPLD and not a small micro is partly to get back up to speed with programmable logic, which I haven't done since the DOS days.

I'll call Xilinx today and get them to let me install WebPack on a Windows box.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Yup, that was it, thanks. That's pretty weird, since I ran "lock pins", which automatically generated a UCF file, and then just changed the pin numbers without changing anything else, including the formatting.

However, it seems to more or less work now, thanks again. Next puzzle is how to get the Digilent plug-in to work.

Cheers

Phil

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Yes, I found the libstdc++.so.5 dependency by looking at the console error messages. (This is the bash console that ISE is running under, not the console window on the GUI, which gave no indication of a problem.)

Thanks

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

We keep talking about picking a CPLD to stock, for little jobs between discrete logic and FPGAs. A couple of the Altera parts look interesting, actually small FPGAs with onboard flash, for a couple of bucks. The Altera "cplds" are sea-of-gates architectures with a bit of RAM, unlike classic cplds that are sum-of-product widgets. It's all VHDL anyhow.

I used to program FPGAs, but the tools have become so complex that now I have people do it for me, people that battle Xilinx or Altera tools full time. We negotiate the logic architecture and they make it work, test bench and all. I used to work on my own car too, back when cars were simple and I was cheap.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation
Reply to
John Larkin

The XC9572XL running 3.3V on both supplies seems like good medicine for a lot of the stuff I do. This one is in a 44-PLCC, which is convenient for hand-soldering if my somewhat hit-or-miss reflow procedure has issues.

I like programmable logic for sequencers that have to have good timing properties, such as this one. I used to use the DOS Orcad PLD tools a lot in prototyping stuff, and occasionally in real jobs.

The aesthetic limit to the number of MSI packages you can use is about 5 or 6 at most, ISTM, which is why I'm doing this now rather than some other time. It'll be nice to be able to set the number of periods for integration using DIP switches, for one thing.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Okay, I have another one.

The Xilinx documents are full of lies. (Or maybe they're hoaxes as in John Brookes's science thread.) ;)

The XC9500XL .rpt file shows unused pins with keepers on them, and their constraints document says that you can put KEEPER or PULLUP on the NET lines.

However, if I put keepers or pullups in the UCF file, it complains that the attribute is "not available with the current device."

Any idea what the skinny is on pullups/pulldowns/keepers on the 9500XL devices? I need to use a couple of dip switches, so it would be useful to know.

Thanks

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Den torsdag den 17. april 2014 20.49.39 UTC+2 skrev Phil Hobbs:

I believe the 9500xl only have pullups, that are on by default you can turn them off but it is all pins or no pins

and the inputs always have weak keepers

-Lasse

Reply to
Lasse Langwadt Christensen

this is for Vivado on ubuntu but I'd think it should help

formatting link

-Lasse

Reply to
Lasse Langwadt Christensen

shouldn't be necessary to call them, just install ISE, pull up the licensing site and move the license to the new host, I think you can do it five time before they start asking questions and it'll keep working on all the hosts

-Lasse

Reply to
Lasse Langwadt Christensen

Den torsdag den 17. april 2014 20.49.39 UTC+2 skrev Phil Hobbs:

I believe the 9500xl always have weak keepers, no pulldowns only pullups, they are on by default and you can only turn them on/off globally for all pins

-Lasse

Reply to
Lasse Langwadt Christensen

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