Hi, all,
Another one that's probably covered somewhere in the docs, but that I can't find there, and a bit of googling has come up with zilch.
I'm trying to get ISE 14.6 to assign CPLD pins in some vaguely rational way, e.g. not scattering wires in the same bus all over the place.
I ran the Lock Pins utility, which generated a UCF file with the right syntax. I then edited the pin placements to suit, and recompiled. The pins were different from before, but still nothing like mine, and no errors or warnings generated.
The floor plan generator doesn't seem to work properly, at least with this device. Double clicking on "Floorplan IO - Pre-Synthesis" brings up a dialogue box that asks to make a new UCF file, but after getting permission, the floor plan editor never comes up.
(OS is 64-bit Linux, CentOS 6.5, which is one they claim to support.)
Any wisdom? If this doesn't sound normal, I'll take it up with Xilinx, but hopefully somebody round here can help, because I'm up to my eyeballs in work at the moment.
Thanks
Phil Hobbs
============
// UCF file for BoxcarLockIn in XC9572XL-10PC44C (44 pin PLCC) #PINLOCK_BEGIN
#Wed Apr 16 16:32:05 2014
NET "Clock" LOC =" S:PIN=5"; NET "Go" LOC =" S:PIN=1"; NET "CW" LOC =" S:PIN=2"; NET "Rst" LOC =" S:PIN=3"; NET "TermCount" LOC =" S:PIN=6"; NET "TermCount" LOC =" S:PIN=7"; NET "TermCount" LOC =" S:PIN=9"; NET "TermCount" LOC =" S:PIN=9"; NET "LED" LOC =" S:PIN=33"; NET "Switch" LOC =" S:PIN=24"; NET "Switch" LOC =" S:PIN=25"; NET "Switch" LOC =" S:PIN=26"; NET "Switch" LOC =" S:PIN=27"; NET "Sample" LOC =" S:PIN=43"; NET "DataReady" LOC =" S:PIN=28"; NET "TermCount" LOC =" S:PIN=11"; NET "TermCount" LOC =" S:PIN=12"; NET "TermCount" LOC =" S:PIN=13"; NET "TermCount" LOC =" S:PIN=14";
#PINLOCK_END