Hi all, This is a really trivial question, but I just can't seem to think correctly, so I thought I'll throw this out here. I am building a non-coherent DPSK receiver in the FPGA. Its all 2's complement arithmetic. Two 12*12 multiplers with an adder that adds the result of the multiplies (matched filter implementation). Then I have a moving average filter which basically boils down to 10 adders (all signed) which adds 10 samples of 24 bit data(result of the adder post multiplication)
I use the result of the moving average filter to decode the data. I have two questions
- In 2's complement arithmetic, do I need to handle the overflow issues when multiplying and adding (i thought you could safely ignore the overflow in 2's complement). If I do, how?
- Does anyone have a good idea for a data decoding scheme. Right now I am using the "poor man's" detection scheme of deciding a bit based on the sign bit of the moving average sum and its not giving me the required fidelity?
Thes questions may sound a little cryptic but any help would be appreciated. Thanks MORPHEUS