DPSK Receiver in Vertex-4

Hi all, This is a really trivial question, but I just can't seem to think correctly, so I thought I'll throw this out here. I am building a non-coherent DPSK receiver in the FPGA. Its all 2's complement arithmetic. Two 12*12 multiplers with an adder that adds the result of the multiplies (matched filter implementation). Then I have a moving average filter which basically boils down to 10 adders (all signed) which adds 10 samples of 24 bit data(result of the adder post multiplication)

I use the result of the moving average filter to decode the data. I have two questions

  1. In 2's complement arithmetic, do I need to handle the overflow issues when multiplying and adding (i thought you could safely ignore the overflow in 2's complement). If I do, how?
  2. Does anyone have a good idea for a data decoding scheme. Right now I am using the "poor man's" detection scheme of deciding a bit based on the sign bit of the moving average sum and its not giving me the required fidelity?

Thes questions may sound a little cryptic but any help would be appreciated. Thanks MORPHEUS

Reply to
morpheus
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Hi Morpheus, I am not an expert on DPSK, but I can answer your first question. Two's complement multiplication does not require normalization [vs. unsigned multiplication in say floating point]. Howeve a MACC (Multiply Accumulate] could eventually overflow. It really depends on the number of Multiply-Accumulate operations. In a Virtex4 DSP48, you have a 48 Bit accumulator - and so for a 12x12 Filter each multiply will produce 24 bits and so you will have 24 guardbits in the DSP48. That should be more than enough - since even a

1024 tap filter will require 10 guard bits after the multiply. If you are instantiating remember that the 12 bits going in to the DSP48 have to be sign extended all the way up to 18 bits.

So in your case you probably don't need to worry about overflow - but you should probably change your code to keep the MSB of the MACC (and round or truncate the LSB). You can also keep more bits than your input datawidth. So if you have a 12x12 Filter with say 64 taps - your result is actually going to be 30 bits (the lowest 30 out of the 48 coming out of the DSP48 - the rest of the outputs will all be sign extended bits). How many of these bits you want to keep for the subsequent adders is up to your accuracy requirements and DPSK. Once you have all of your filter results you could also choose to keep all 30 bits - and add the 30 bit numbers in other DSP48's and then round/truncate only at the end of your last add operation.

By the way as long as you sign extend to your desired number of bits - there is no difference between a signed adder and an unsigned adder. The DSP48 signextends the multiplier result internally before going to the 48-bit Accumulator for MACC's.

- Vic

morpheus wrote:

Reply to
Vic Vadi

Thanks Vic, your advice was quite reassuring. I solved the problem. The DSP48 slice automatically sign extends the data going into the slice. The 24-bits coming out of the multiplier are sign-extended to 28-bits when I add the results of the multiplier. This is giving me enough resolution to maintain the fidelity of demodulated output. Thanks MORPHEUS

Reply to
morpheus

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