Hi all, I am looking for an OPB to wishbone bridge to let OPB talk to my IP via wishbone in EDK. I have read some posts on OPB-> wishbone wrapper (available at opencores.org). Had a look at the wrapper, which raises a couple of questions in my mind. Where is the OPB bus translation to wishbone bus taking place in this wrapper? How to use it in an environment where the IP is connected to the wishbone slave and the wishbone slave has to be read and written by the OPB from the microblaze side? To start with, lets take the example that the wishbone slave is connected to SRAM at the other end and the microblaze writes and reads the SRAM via opb-> wishbone interface. In this scenario, how would this opb->wishbone wrapper help.
will be waiting for a reply................
Farhan
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J
jetmarc
Hi Farhan,
My experience with this wrapper was not a good one.
It won't bridge a memory controller for you, because it has an (undocumented) limit of only working in the address range
0x80000000-0x800000ff. It won't signal SI_ToutSup either, resulting in another hard-to-meet timing requirement on your memory controller.
I tried to use the bridge to interface with a wishbone ATA host (also from opencores). It sort-of worked, but it was far from satisfying. Reading the OPB IPIF specs I realized that most signals map one-to-one with WB. It was a piece of cake to connect the wishbone peripherial directly to the OPB IPIF, without bridge. Faster, cheaper, better.
Regards, Marc
S
sheikh.m.farhan
Hi Marc, Did you get my reply to your answer? I replied to your answer on the group but I dont see my reply appearing here. I sent my reply to you directly by using the 'Reply to Author' option. I hope you received it.
waiting for some more help from you.
Regards Farhan
S
sheikh.m.farhan
-------------------------------------------------------------------------------------------------------------------------- Since my last reply appeared on the group, let me post my 'lost' reply once again.
------------------------------------------------------------------------------------------------------------------------- "Marc, what you are saying is, I should throw away the OPB-> wishbone wrapper and directly connect the OPB IPIF signals to wishbone (slave, in my case) signals. Could you kindly give me more details on which IPIF signal to connect with wishbone slave signals. Following is a list of the wishbone slave signals that have to talk to OPB via IPIF.
I hope I am making some sense here while asking for more details :)
Regards Farhan
J
jetmarc
Hi Farhan,
Here's how I wired the wishbone ATA controller to the OPB IPIF. I hope it helps.
--- OPB2IPIF
signal sig_o2i_Clk_o : std_logic; -- opb2ipif_0 signal sig_o2i_Reset_o : std_logic; signal sig_o2i_Freeze_o : std_logic; signal sig_o2i_AddrValid_o : std_logic; signal sig_o2i_Burst_o : std_logic; signal sig_o2i_RNW_o : std_logic; signal sig_o2i_CS_o : std_logic_vector(0 to 0); signal sig_o2i_CE_o : std_logic_vector(0 to 0); signal sig_o2i_RdCE_o : std_logic_vector(0 to 0); signal sig_o2i_WrCE_o : std_logic_vector(0 to 0); signal sig_o2i_Ack_i : std_logic; signal sig_o2i_Retry_i : std_logic; signal sig_o2i_Error_i : std_logic; signal sig_o2i_ToutSup_i : std_logic; signal sig_o2i_PostedWrInh_i : std_logic; signal sig_o2i_AddrAck_i : std_logic;
signal sig_o2i_Addr_o_xil : std_logic_vector(0 to 31); signal sig_o2i_Data_o_xil : std_logic_vector(0 to 31); signal sig_o2i_BE_o_xil : std_logic_vector(0 to 3); signal sig_o2i_Data_i_xil : std_logic_vector(0 to 31);
signal sig_o2i_Addr_o : std_logic_vector(31 downto 0); signal sig_o2i_Data_o : std_logic_vector(31 downto 0); signal sig_o2i_BE_o : std_logic_vector( 3 downto 0); signal sig_o2i_Data_i : std_logic_vector(31 downto 0);
--- WISHBONE bus
signal sig_wb_data_o : std_logic_vector (31 downto 0); signal sig_wb_data_i : std_logic_vector (31 downto 0); -- signal sig_wb_addr_o : std_logic_vector (31 downto 0); signal sig_wb_cyc_o : std_logic; signal sig_wb_stb_o : std_logic; signal sig_wb_sel_o : std_logic_vector ( 3 downto 0); signal sig_wb_we_o : std_logic; signal sig_wb_ack_i : std_logic; signal sig_wb_err_i : std_logic; signal sig_wb_rty_i : std_logic;
--- Components
component edk port (
...
o2i_Clk_o_pin : out std_logic; -- opb2ipif_0 (for ATAHOST) o2i_Reset_o_pin : out std_logic; o2i_Freeze_o_pin : out std_logic; o2i_Addr_o_pin : out std_logic_vector(0 to 31); o2i_AddrValid_o_pin : out std_logic; o2i_Data_o_pin : out std_logic_vector(0 to 31); o2i_BE_o_pin : out std_logic_vector(0 to 3); o2i_Burst_o_pin : out std_logic; o2i_RNW_o_pin : out std_logic; o2i_CS_o_pin : out std_logic_vector(0 to 0); o2i_CE_o_pin : out std_logic_vector(0 to 0); o2i_RdCE_o_pin : out std_logic_vector(0 to 0); o2i_WrCE_o_pin : out std_logic_vector(0 to 0); o2i_Data_i_pin : in std_logic_vector(0 to 31); o2i_Ack_i_pin : in std_logic; o2i_Retry_i_pin : in std_logic; o2i_Error_i_pin : in std_logic; o2i_ToutSup_i_pin : in std_logic; o2i_PostedWrInh_i_pin : in std_logic; o2i_AddrAck_i_pin : in std_logic;
...
); end component;
------------------------------------------------------------------- --- DISK --- -------------------------------------------------------------------
--- signals
signal sig_disk_irq : std_logic; -- disk module requests INTERRUPT signal sig_disk_dma_req : std_logic; -- disk module requests DMA signal sig_disk_dma_ack : std_logic;
--- external pin glue
signal sig_disk_reset_n : std_logic; signal sig_disk_dd_i : std_logic_vector (15 downto 0); signal sig_disk_dd_o : std_logic_vector (15 downto 0); signal sig_disk_dd_t : std_logic; signal sig_disk_dd_oe : std_logic; signal sig_disk_da : std_logic_vector ( 2 downto 0); signal sig_disk_cs0_n : std_logic; signal sig_disk_cs1_n : std_logic; signal sig_disk_dior_n : std_logic; signal sig_disk_diow_n : std_logic; signal sig_disk_iordy : std_logic; signal sig_disk_intrq : std_logic; signal sig_disk_dmarq : std_logic; signal sig_disk_dmack_n : std_logic;
signal sig_disk_dasp_n : std_logic; -- not used signal sig_disk_pdiag_n : std_logic; -- not used
--- core glue
signal sig_disk_da_u : unsigned(2 downto 0);
signal sig_wb_addr_disk_u : unsigned(6 downto 2); signal sig_wb_cs_disk : std_logic;
wb_clk_i : in std_logic; -- master clock in arst_i : in std_logic := '1'; -- asynchronous active low reset wb_rst_i : in std_logic := '0'; -- synchronous active high reset
-- WISHBONE SLAVE signals
wb_cyc_i : in std_logic; -- valid bus cycle input wb_stb_i : in std_logic; -- strobe/core select input wb_ack_o : out std_logic; -- strobe acknowledge output wb_rty_o : out std_logic; -- retry output wb_err_o : out std_logic; -- error output wb_adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected -- A5 = '1' CS1- asserted, '0' CS0- asserted -- A4..A2 ATA address lines -- A6 = '0' ATA controller selected wb_dat_i : in std_logic_vector(31 downto 0); -- Databus in wb_dat_o : out std_logic_vector(31 downto 0); -- Databus out wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select signals wb_we_i : in std_logic; -- Write enable input wb_inta_o : out std_logic; -- interrupt request signal IDE0
-- DMA engine signals
DMA_req : out std_logic; -- DMA request DMA_Ack : in std_logic; -- DMA acknowledge
-- ATA signals
resetn_pad_o : out std_logic; dd_pad_i : in std_logic_vector(15 downto 0); dd_pad_o : out std_logic_vector(15 downto 0); dd_padoe_o : out std_logic; da_pad_o : out unsigned(2 downto 0); cs0n_pad_o : out std_logic; cs1n_pad_o : out std_logic;
diorn_pad_o : out std_logic; diown_pad_o : out std_logic; iordy_pad_i : in std_logic; intrq_pad_i : in std_logic;
dmarq_pad_i : in std_logic; dmackn_pad_o : out std_logic;
debug_pio_sample_indata : out std_logic ); end component;