I'm working with XILINX ise 9.2i; designing a deserializer & using 2 DCM's in sequence to generate 4 100MHz clocks (each 90 degrees out of phase) from the 50MHz local clock on a Spartan-3 FPGA
The error i'm getting:
ERROR:NgdBuild:455 - logical net 'CLK100X' has multiple driver(s): pin CLK2X on block clockdoubler/DCM_INST with type DCM, pin PAD on block CLK100X with type PAD
regarding the following code:
dcm1 clockdoubler ( .CLKIN_IN(CLKIN), //50MHz local spartan-3 clock .RST_IN(RST), .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT1), .CLK0_OUT(CLK0), .CLK2X_OUT(CLK100X), //100MHz clock out .LOCKED_OUT(LOCKED1) );
dcm2 clockseparater ( .CLKIN_IN(CLK100X), //100MHz input .RST_IN(LOCKED1), .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT2), .CLK0_OUT(CLK100A), //0 phase diff .CLK90_OUT(CLK100B), //90 deg .CLK180_OUT(CLK100C), //180 deg .CLK270_OUT(CLK100D), //270 deg .LOCKED_OUT(LOCKED2), .STATUS_OUT(STATUS2) );
For the i changed the buffered output of the first DCM to be "local routing" instead of a global buf, which i know can cause this same error message, but im still getting the error... i have no idea whats wrong with it, any help would be greatly appreciated! Thanks