I'm working on a Virtex-4 FX12LC Design with PPC405 Core, SDRAM and Multiport Memory Controller 2 (MPMC2 release 2006/08/31). The Memec Development Board contains the Infineon DDR SDRAM HYB25D512160BC-6 (64 Mbyte, Databus 16 bit). I started the Design with BSB and OPB_DDR_CNTLR, then replaced the DDR_CNTLR with the MPMC2 Core of from "ml403_ddr_p_100mhz" and changed the Memory Width to 16 bit, Pin Constraints etc. The MPMC2 is configured to hold only one PLB connection, the remaining 7 ports are set to "None". After the project was built, I tried to access the SDRAM Memory via a simple C Application or XMD. The problem now is, that the memory content seems to be mirrored every 32 bit. For example, when I write at address 0x00000000 a 32 bit value 0xA5A5A5A5, the same value appears at address 0x00000008. The same behavior between addresses 0x00000004 and 0x0000000C.
It looks like:0x00000000: 0xA5A5A5A5 0x00000000 0xA5A5A5A5 0x00000000 0x00000010: 0x00000000 0xDEADBEEF 0x00000000 0xDEADBEEF 0x00000020: 0x00001111 0x00002222 0x00001111 0x00002222 0x00000030: 0x00000000 0x00000000 0x00000000 0x00000000
The MPMC Part in system.mhs:
BEGIN mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6 PARAMETER INSTANCE = mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6_0 PARAMETER HW_VER = 1.04.a PARAMETER C_PLB_0_BASEADDR = 0x0000_0000 PARAMETER C_PLB_0_HIGHADDR = 0x03ff_ffff PARAMETER C_PLB_0_PLB_NUM_MASTERS = 2 PARAMETER C_PLB_0_PLB_MID_WIDTH = 1 PARAMETER C_PLB_0_PI_TO_MPMC2_CLK_RATIO = 1 PARAMETER C_PLB_0_MPMC2_TO_PI_CLK_RATIO = 1 PARAMETER C_PLB_0_BRIDGE_TO_PI_CLK_RATIO = 1 BUS_INTERFACE PLB_S_0 = plb PORT MPMC2_0_Rst = sys_bus_reset PORT PLB_0_PLB_SlClk = CLK_100MHz PORT MPMC2_0_Clk0_2X = net_gnd PORT MPMC2_Slowest_Clk = CLK_100MHz PORT MPMC2_0_Clk0 = CLK_100MHz PORT MPMC2_0_Clk90 = CLK_100MHz_90 PORT MPMC2_0_Clk_Cal = CLK_100MHz PORT MPMC2_0_Clk_200MHz = CLK_200MHz PORT MPMC2_0_Clk_Mem = CLK_100MHz_90 PORT MPMC2_0_DDR_Clk_O = DDR_Clk PORT MPMC2_0_DDR_Clk_n_O = DDR_Clkn PORT MPMC2_0_DDR_CE_O = DDR_CKE PORT MPMC2_0_DDR_BankAddr_O = DDR_BA PORT MPMC2_0_DDR_Addr_O = DDR_Addr PORT MPMC2_0_DDR_CS_n_O = DDR_CSn PORT MPMC2_0_DDR_RAS_n_O = DDR_RASn PORT MPMC2_0_DDR_CAS_n_O = DDR_CASn PORT MPMC2_0_DDR_WE_n_O = DDR_WEn PORT MPMC2_0_DDR_DQ = DDR_DQ PORT MPMC2_0_DDR_DQS = DDR_DQS PORT MPMC2_0_DDR_DM = DDR_DM END
The MPMC parameters are equal to the reference design "v4fx12lc_ddr_idpp_100mhz", except the parameters which setup the number of master/slaves, and of course the datawidth of memory. I checked the pin constraints, they are ok. So where could be the mistake? Are there any MPMC Parameters which I forgot to set correctly? Do I need to modify PLB Settings?
Are there any suggestions or hints? Thanks in advance. Mack