Xilinx EDK GPIO: Can I drive internal logic with it?

Hi all,

I have an OPB_GPIO module configured as all outputs. It is a part of an EDK system which is instantiated as a module in a top-level ISE project. I am using d_outs from the GPIO module. When I tried inserting some logic between these outputs and the top level pins I got the following error:

ERROR:NgdBuild:809 - output pad net 'gpio_leds' has an illegal load: pin I2 on block _n00141 with type LUT3

So, does that mean that I can't drive any internal logic with GPIO outputs?

Thanks, /Mikhail

Reply to
MM
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GPIO outputs can drive internal logic. Sometimes it's easier than building an IPIF interface. I'm going to take a guess and say that you connected your internal logic input to the IOB instead of to the GPIO.

Post the code if you want someone to figure it out.

--
Joe Samson
Pixel Velocity
Reply to
Joseph Samson

Here it goes (with most of the unrelated stuff deleted):

entity top is Port ( Led : out std_logic_vector(12 downto 1); );

end top;

architecture top_rtl of top is

component system_stub is port ( -- skip -- fpga_0_GPIO_LED_d_out_pin : out std_logic_vector(0 to 19); -- skip -- ); end component;

signal gpio_leds : std_logic_vector(0 to 19); signal led_tick : std_logic;

begin

PPC_INST: system_stub port map ( -- skip -- fpga_0_GPIO_LED_d_out_pin => gpio_leds, -- skip -- );

LED_GEN: for i in 0 to 7 generate Led(i+1)

Reply to
MM

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