This is an all VHDL design. Modelsim XE is installed as full VHDL. Design uses a number of block rams built with Xilinx coregen, which produces the VDHL and Verilog files along with a bunch of other files.
Here's the problem that started showing up with ISE 8.1i webpack and is still there with ISE 8.2 full (not the webpack):
When I first fire up the simulation, Modelsim sees the verilog files and puts them in the Modelsim work workspace (thinking that they are part of the design I would guess). Then it proceeds to compile a bunch of stuff and then fails because Modelsim XE does not support a mixed design with both VHDL and Verilog. If I then remove the verilog files from the project, and delete them out of the Modelsim work workspace, the next time I fire up Modelsim everything runs fine. - If the fix was just to delete the verilog files I could live with that, but there's more...
If I delete the verilog files before Modelsim has EVER run on this project, Modelsim fails immediately saying the verilog files are missing from the project directory and refuses to do anything until they are put back in the project directory. So the verilog files have to be there so Modelsim can run the first time (which does a bunch of stuff and then errors out for a mixed design) and then the verilog files have to be removed so Modelsim will run correctly.
Can someone tell me what's going on? This problem never showed up until Xilinx ISE 8.1 (which I was running with Modelsim XE 5.5) and its still there with my new upgrade to Xilinx ISE 8.2i and Modelsim XE 6.1e. Note that I was also running Modelsim XE 5.5 when I was back at Xilinx ISE 6.2i and the problem was not present then.